topic IMX7S generic timer register base address in i.MX Processors

IMX7S generic timer register base address

alexjun — Wed, 11 Jul 2018 04:00:43 GMT

Hi,

Could you help point out where I can find register base address for generic timer? IMX7S reference manual mentioned below two timer, but no register address can be found. Only ARM Peripherals start address can be found in memory map chapter. ARM reference manual have register description, but no address neither.

One local generic timer integrated into each Cortex-A7 CPU
Global system counter with timer bus interface to Cortex-A7 MPCore generic timers

Thank you in advance!

Jun

Re: IMX7S generic timer register base address

igorpadykov — Wed, 11 Jul 2018 05:50:15 GMT

Hi Alex

description and usage of generic timer can be found in arm (www.arm.com) documentation:

from Cortex-A7 MPCore Technical Reference Manual - ARM Infocenter, sect.9.3 Timer programmers model

Within each processor, a set of Timer registers are allocated to the CP15 coprocessor space.

http://infocenter.arm.com/help/topic/com.arm.doc.ddi0464d/DDI0464D_cortex_a7_mpcore_r0p3_trm.pdf

Best regards
igor
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Re: IMX7S generic timer register base address

falstaff — Wed, 11 Jul 2018 14:58:50 GMT

The generic timer also has a memory mapped interface. It is documented as "System Counter_CTRL" in the i.MX 7 Reference Manual. E.g. upstream U-Boot uses the interface to initialize the timer, see arch/arm/mach-imx/syscounter.c and arch/arm/include/asm/arch-mx7/imx-regs.h (SCTR_BASE_ADDR).

Re: IMX7S generic timer register base address

alexjun — Thu, 12 Jul 2018 08:53:09 GMT

Thank you! So the generic timer is the system counter, just different name.