topic Regarding DDR Line Swapping in i.Mx6ULL in i.MX Processors https://community.nxp.com/t5/i-MX-Processors/Regarding-DDR-Line-Swapping-in-i-Mx6ULL/m-p/801599#M123861 <HTML><HEAD></HEAD><BODY><P><SPAN style="background-color: white; background-repeat: initial; background-size: initial; background-clip: initial; background-attachment: initial; font-size: small; font-family: Arial, sans-serif; background-image: initial; background-origin: initial; background-position: initial;">Hi,</SPAN></P><P></P><P><SPAN style="background-color: white; background-repeat: initial; background-size: initial; background-clip: initial; background-attachment: initial; font-size: small; font-family: Arial, sans-serif; background-image: initial; background-origin: initial; background-position: initial;">As mentioned in the i.MX6ULL Reference Manual, we have swapped the DDR Data lines. <BR /> <BR />But we would like to know if there are any configuration change in Software. <BR /> <BR />The Note in the i.MX6ULL Reference Manual refers as below, <BR />when byte lane swapping was done target DDR IC register read value must be transposed according data line swapping. <BR /> <BR />Please let us know on how to configure the DDR IC Register read value according to our swapped values. <BR /> </SPAN></P><P></P><P><SPAN style="background-color: white; background-repeat: initial; background-size: initial; background-clip: initial; background-attachment: initial; font-size: small; font-family: Arial, sans-serif; background-image: initial; background-origin: initial; background-position: initial;">Regards,</SPAN></P><P><SPAN style="background-color: white; background-repeat: initial; background-size: initial; background-clip: initial; background-attachment: initial; font-size: small; font-family: Arial, sans-serif; background-image: initial; background-origin: initial; background-position: initial;">Geetha</SPAN></P></BODY></HTML> Mon, 05 Nov 2018 05:34:51 GMT Geetharajammal 2018-11-05T05:34:51Z Regarding DDR Line Swapping in i.Mx6ULL https://community.nxp.com/t5/i-MX-Processors/Regarding-DDR-Line-Swapping-in-i-Mx6ULL/m-p/801599#M123861 <HTML><HEAD></HEAD><BODY><P><SPAN style="background-color: white; background-repeat: initial; background-size: initial; background-clip: initial; background-attachment: initial; font-size: small; font-family: Arial, sans-serif; background-image: initial; background-origin: initial; background-position: initial;">Hi,</SPAN></P><P></P><P><SPAN style="background-color: white; background-repeat: initial; background-size: initial; background-clip: initial; background-attachment: initial; font-size: small; font-family: Arial, sans-serif; background-image: initial; background-origin: initial; background-position: initial;">As mentioned in the i.MX6ULL Reference Manual, we have swapped the DDR Data lines. <BR /> <BR />But we would like to know if there are any configuration change in Software. <BR /> <BR />The Note in the i.MX6ULL Reference Manual refers as below, <BR />when byte lane swapping was done target DDR IC register read value must be transposed according data line swapping. <BR /> <BR />Please let us know on how to configure the DDR IC Register read value according to our swapped values. <BR /> </SPAN></P><P></P><P><SPAN style="background-color: white; background-repeat: initial; background-size: initial; background-clip: initial; background-attachment: initial; font-size: small; font-family: Arial, sans-serif; background-image: initial; background-origin: initial; background-position: initial;">Regards,</SPAN></P><P><SPAN style="background-color: white; background-repeat: initial; background-size: initial; background-clip: initial; background-attachment: initial; font-size: small; font-family: Arial, sans-serif; background-image: initial; background-origin: initial; background-position: initial;">Geetha</SPAN></P></BODY></HTML> Mon, 05 Nov 2018 05:34:51 GMT https://community.nxp.com/t5/i-MX-Processors/Regarding-DDR-Line-Swapping-in-i-Mx6ULL/m-p/801599#M123861 Geetharajammal 2018-11-05T05:34:51Z Re: Regarding DDR Line Swapping in i.Mx6ULL https://community.nxp.com/t5/i-MX-Processors/Regarding-DDR-Line-Swapping-in-i-Mx6ULL/m-p/801600#M123862 <HTML><HEAD></HEAD><BODY><P>Hello Geetha,</P><P></P><P>No software changes are required if you are using NXP’s BSP, as this BSP does not read the DDR memory mode register.</P><P></P><P>I hope this helps.</P><P>Regards,</P></BODY></HTML> Tue, 06 Nov 2018 18:10:32 GMT https://community.nxp.com/t5/i-MX-Processors/Regarding-DDR-Line-Swapping-in-i-Mx6ULL/m-p/801600#M123862 gusarambula 2018-11-06T18:10:32Z