i.MX ProcessorsのトピックRe: i.MX31 SDHC input setup/hold timing

i.MX31 SDHC input setup/hold timing

sugiyamatoshihi — Fri, 07 Sep 2018 02:39:43 GMT

Hi,

Does some one know the SDHC spec. of i.MX31?

There are input setup/hold time of SDHC in data sheet. However, it specify max value of setup/hold time like below.

SDHC input setup MAX 18.5nS, SDHC input hold MAX -11.5nS.

Usually, setup/hold time should be minimum value not MAX.

Could you teach min value of setup/hold time?

Best Regards,

Sugiyama

Yuri — Fri, 07 Sep 2018 05:48:32 GMT

Hello,

Parameters SD7 and SD8 are defined in the i.MX31 specs with regard to the failing CLK.

SD specs assume rising ones; so min values of SD7 and SD8 are calculated as

CLK period / 2 - SD7/8.

Have a great day,

Yuri

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sugiyamatoshihi — Fri, 07 Sep 2018 07:00:47 GMT

Hi, Yuri,

Thank you for quick reply.

If it is CLK period/2 - SD7/8, it depend on frequency, but I think setup/hold timing are fixed value.

Does it aware only 25MHz clock and use that value for other frequency?

I calculated them at 25MHz, 40nS cycle

Does it mean setup is 1.5nS min and hold is 8.5nS min?

Does this use for all frequency?

Best Regards,

Sugiyama

Yuri — Fri, 07 Sep 2018 07:14:27 GMT

Generally You are right: setup is 1.5nS min, hold is 8.5nS min for all frequencies.

~Yuri.