<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>i.MX ProcessorsのトピックRe: Does the I.MX8M support eCSPI3?</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Does-the-I-MX8M-support-eCSPI3/m-p/801281#M123794</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Mike,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Yes The ECSPI 3 is muxed with UART 1 and UART 2.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 01 Oct 2018 14:28:31 GMT</pubDate>
    <dc:creator>Bio_TICFSL</dc:creator>
    <dc:date>2018-10-01T14:28:31Z</dc:date>
    <item>
      <title>Does the I.MX8M support eCSPI3?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Does-the-I-MX8M-support-eCSPI3/m-p/801280#M123793</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Does the I.MX8M support&amp;nbsp;eCSPI3? Page 8 of the Datasheet says so, but the associated functionality isn't listed in the contact assignments (Table 83).&lt;/P&gt;&lt;P&gt;However, the Reference Manual shows it muxed into both UART1 and UART2.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 26 Sep 2018 22:48:32 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Does-the-I-MX8M-support-eCSPI3/m-p/801280#M123793</guid>
      <dc:creator>mike_james</dc:creator>
      <dc:date>2018-09-26T22:48:32Z</dc:date>
    </item>
    <item>
      <title>Re: Does the I.MX8M support eCSPI3?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Does-the-I-MX8M-support-eCSPI3/m-p/801281#M123794</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Mike,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Yes The ECSPI 3 is muxed with UART 1 and UART 2.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 01 Oct 2018 14:28:31 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Does-the-I-MX8M-support-eCSPI3/m-p/801281#M123794</guid>
      <dc:creator>Bio_TICFSL</dc:creator>
      <dc:date>2018-10-01T14:28:31Z</dc:date>
    </item>
  </channel>
</rss>

