i.MX ProcessorsのトピックRe: MIPI_DSI timing setting

MIPI_DSI timing setting

janmennen — Fri, 14 Dec 2018 15:57:14 GMT

Hello

I have difficulty in finding the write settings to drive a panel with resolution 1344x1760. This panel is connected via TI MIPI to LVDS bridge.

After a lot of trail and error i find a timing which gives valid output. Clock frequency is however only 80 MHz
When increasing the clock to 100 MHz i get still valid hsync pulses but no vsync. Because i still get the hsync i assume it is not a timing problem

I see also that when i increase the vertical frontporch to 20 i don't get any valid MIPI signal anymore.

Question is how can i define the correct setting for a given resolution and are there restrictions in vertical and horizontal blanking setting?

This is current setting. The target is to drive with higher clock up to 145 MHz to get 60 Hz frame rate

static const struct drm_display_mode cid_cid1344_mode = {
.clock = 80000,
.hdisplay = 1344,
.hsync_start = 1344 + 20,
.hsync_end = 1344 + 20 + 40,
.htotal = 1344 + 20 + 40 + 120,
.vdisplay = 1760,
.vsync_start = 1760 + 2,
.vsync_end = 1760 + 2 + 4,
.vtotal = 1760 + 2 + 4 + 2,
.vrefresh = 30,
.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
};

Thanks Jan

Re: MIPI_DSI timing setting

igorpadykov — Sat, 15 Dec 2018 03:53:47 GMT

Hi jan

for mipi-dsi bridge example one can check:

how to use ldb/lvds in android8 of imx8mq ?

Also one can look at example in ..drivers\gpu\drm\panel\panel-raydium-rm67191.c

panel-raydium-rm67191.c\panel\drm\gpu\drivers - linux-imx - i.MX Linux kernel

and try to debug it, when the bridge chip is found and initialized, it will enable the clocks,
then call detect function to get the supported video modes.
Display system will set one of the modes to LCDIF/DCSS and bridge driver,
the display clock is enabled at this time.

Best regards
igor
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Re: MIPI_DSI timing setting

janmennen — Fri, 21 Dec 2018 16:29:45 GMT

Hello Igor

When using 132 MHz clock i get valid mipi timing.
i used following settting

.clock = 132000,
.hdisplay = 1344,
.hsync_start = 1344 + 20,
.hsync_end = 1344 + 20 + 2,
.htotal = 1344 + 20 + 2 + 34,
.vdisplay = 1760,
.vsync_start = 1760 + 2,
.vsync_end = 1760 + 2 + 2,
.vtotal = 1760 + 2 + 2 + 2,
.vrefresh = 60,

However the horizontal timing is different then calculated from blanking setting.
According the calculation line time should be 9.65 us but i measure 11.68us
Frame frequency is 48.4 Hz instead of 58.8

The problem now is that when i increase the clock frequency and set it to 144 MHz i don't get valid MIPI output
Seems to me that blanking parameter is dependent on the clockfrequency.
Do you know what the relation is and how the LP period is inserted in the horizontal blanking.

Thanks Jan