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    <title>i.MX ProcessorsのトピックIssue with ptp hardware timestamp imx6</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Issue-with-ptp-hardware-timestamp-imx6/m-p/800077#M123655</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I'm trying to sync the clock b/w 2 imx6dl boards with hardware and software time stamping. I have followed the below link and able to sync the clock with software time stamping.&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="http://linuxptp.sourceforge.net/" title="http://linuxptp.sourceforge.net/"&gt;The Linux PTP Project&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;With ethtool, i can see that it supports both software and hardware timestamp&lt;/P&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;P&gt;root@phyboard-mira-imx6-7:~# ethtool -T eth0&lt;BR /&gt;Time stamping parameters for eth0:&lt;BR /&gt;Capabilities:&lt;BR /&gt; hardware-transmit (SOF_TIMESTAMPING_TX_HARDWARE)&lt;BR /&gt; software-transmit (SOF_TIMESTAMPING_TX_SOFTWARE)&lt;BR /&gt; hardware-receive (SOF_TIMESTAMPING_RX_HARDWARE)&lt;BR /&gt; software-receive (SOF_TIMESTAMPING_RX_SOFTWARE)&lt;BR /&gt; software-system-clock (SOF_TIMESTAMPING_SOFTWARE)&lt;BR /&gt; hardware-raw-clock (SOF_TIMESTAMPING_RAW_HARDWARE)&lt;BR /&gt;PTP Hardware Clock: 0&lt;BR /&gt;Hardware Transmit Timestamp Modes:&lt;BR /&gt; off (HWTSTAMP_TX_OFF)&lt;BR /&gt; on (HWTSTAMP_TX_ON)&lt;BR /&gt;Hardware Receive Filter Modes:&lt;BR /&gt; none (HWTSTAMP_FILTER_NONE)&lt;BR /&gt; all (HWTSTAMP_FILTER_ALL)&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Below is the slaves output with software time stamp&lt;/P&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;P&gt;root@phyboard-mira-imx6-7:~# ptp4l -i eth0 -S -s -m&lt;BR /&gt;ptp4l[726.639]: port 1: INITIALIZING to LISTENING on INIT_COMPLETE&lt;BR /&gt;ptp4l[726.641]: port 0: INITIALIZING to LISTENING on INIT_COMPLETE&lt;BR /&gt;ptp4l[727.116]: port 1: new foreign master 9840bb.fffe.39baf7-1&lt;BR /&gt;ptp4l[727.118]: port 1: new foreign master 502df4.fffe.0b5840-1&lt;BR /&gt;ptp4l[731.116]: selected best master clock 9840bb.fffe.39baf7&lt;BR /&gt;ptp4l[731.116]: foreign master not using PTP timescale&lt;BR /&gt;ptp4l[731.117]: port 1: LISTENING to UNCALIBRATED on RS_SLAVE&lt;BR /&gt;ptp4l[731.118]: selected best master clock 502df4.fffe.0b5840&lt;BR /&gt;ptp4l[731.118]: foreign master not using PTP timescale&lt;BR /&gt;ptp4l[733.118]: master offset -17883708630450 s0 freq -37532 path delay 59668&lt;BR /&gt;ptp4l[734.118]: master offset -17883708586248 s0 freq -37532 path delay 59668&lt;BR /&gt;ptp4l[735.118]: master offset -17883708545313 s0 freq -37532 path delay 52602&lt;BR /&gt;ptp4l[736.118]: master offset -17883708512346 s0 freq -37532 path delay 55504&lt;BR /&gt;ptp4l[737.118]: master offset -17883708478827 s0 freq -37532 path delay 54187&lt;BR /&gt;ptp4l[738.118]: master offset -17883708445625 s0 freq -37532 path delay 54187&lt;BR /&gt;ptp4l[739.119]: master offset -17883708410979 s0 freq -37532 path delay 56078&lt;BR /&gt;ptp4l[740.119]: master offset -17883708370443 s0 freq -37532 path delay 56078&lt;BR /&gt;ptp4l[741.119]: master offset -17883708350767 s0 freq -37532 path delay 55269&lt;BR /&gt;ptp4l[742.119]: master offset -17883708311806 s0 freq -37532 path delay 55843&lt;BR /&gt;ptp4l[743.119]: master offset -17883708277008 s0 freq -37532 path delay 54246&lt;BR /&gt;ptp4l[744.119]: master offset -17883708233138 s0 freq -37532 path delay 54246&lt;BR /&gt;ptp4l[745.119]: master offset -17883708174601 s0 freq -37532 path delay 54246&lt;BR /&gt;ptp4l[746.119]: master offset -17883708163066 s0 freq -37532 path delay 54246&lt;BR /&gt;ptp4l[747.120]: master offset -17883708118787 s0 freq -37532 path delay 55171&lt;BR /&gt;ptp4l[748.120]: master offset -17883708097060 s0 freq -37532 path delay 56978&lt;BR /&gt;ptp4l[749.120]: master offset -17883708060857 s1 freq -1936 path delay 56978&lt;BR /&gt;ptp4l[750.120]: master offset -5123 s2 freq -2453 path delay 56978&lt;BR /&gt;ptp4l[750.120]: port 1: UNCALIBRATED to SLAVE on MASTER_CLOCK_SELECTED&lt;BR /&gt;ptp4l[751.120]: master offset 993 s2 freq -1841 path delay 56978&lt;BR /&gt;ptp4l[752.120]: master offset -7894 s2 freq -2737 path delay 57711&lt;BR /&gt;ptp4l[753.120]: master offset -6826 s2 freq -2637 path delay 57711&lt;BR /&gt;ptp4l[754.120]: master offset -4274 s2 freq -2386 path delay 58463&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;But with hardware time stamp, i'm not able to sync the clock&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;P&gt;root@phyboard-mira-imx6-7:~# ptp4l -i eth0 -s -m&lt;BR /&gt;ptp4l[1084.333]: selected /dev/ptp0 as PTP clock&lt;BR /&gt;ptp4l[1084.336]: port 1: INITIALIZING to LISTENING on INIT_COMPLETE&lt;BR /&gt;ptp4l[1084.337]: port 0: INITIALIZING to LISTENING on INIT_COMPLETE&lt;BR /&gt;ptp4l[1085.822]: port 1: new foreign master 502df4.fffe.0b5840-1&lt;BR /&gt;ptp4l[1089.823]: selected best master clock 502df4.fffe.0b5840&lt;BR /&gt;ptp4l[1089.823]: port 1: LISTENING to UNCALIBRATED on RS_SLAVE&lt;BR /&gt;ptp4l[1091.822]: master offset -17881927778001 s0 freq +0 path delay 0&lt;BR /&gt;ptp4l[1092.822]: master offset -17881927778001 s0 freq +0 path delay 0&lt;BR /&gt;ptp4l[1093.823]: master offset -17881927778001 s0 freq +0 path delay 0&lt;BR /&gt;ptp4l[1094.823]: master offset -17881927778001 s0 freq +0 path delay 0&lt;BR /&gt;ptp4l[1095.823]: master offset -17881927778001 s0 freq +0 path delay 0&lt;BR /&gt;ptp4l[1096.823]: master offset -17881927778001 s0 freq +0 path delay 0&lt;BR /&gt;ptp4l[1097.823]: master offset -17881927778001 s0 freq +0 path delay 0&lt;BR /&gt;ptp4l[1098.823]: master offset -17881927778001 s0 freq +0 path delay 0&lt;BR /&gt;ptp4l[1099.823]: master offset -17881927778001 s0 freq +0 path delay 0&lt;BR /&gt;ptp4l[1100.823]: master offset -17881927778001 s0 freq +0 path delay 0&lt;BR /&gt;ptp4l[1101.823]: master offset -17881927778001 s0 freq +0 path delay 0&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;Is any additional configurations needed for hardware timestamp?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards&lt;/P&gt;&lt;P&gt;khaleel&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 14 Dec 2018 10:51:17 GMT</pubDate>
    <dc:creator>khaleel_s</dc:creator>
    <dc:date>2018-12-14T10:51:17Z</dc:date>
    <item>
      <title>Issue with ptp hardware timestamp imx6</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Issue-with-ptp-hardware-timestamp-imx6/m-p/800077#M123655</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I'm trying to sync the clock b/w 2 imx6dl boards with hardware and software time stamping. I have followed the below link and able to sync the clock with software time stamping.&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="http://linuxptp.sourceforge.net/" title="http://linuxptp.sourceforge.net/"&gt;The Linux PTP Project&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;With ethtool, i can see that it supports both software and hardware timestamp&lt;/P&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;P&gt;root@phyboard-mira-imx6-7:~# ethtool -T eth0&lt;BR /&gt;Time stamping parameters for eth0:&lt;BR /&gt;Capabilities:&lt;BR /&gt; hardware-transmit (SOF_TIMESTAMPING_TX_HARDWARE)&lt;BR /&gt; software-transmit (SOF_TIMESTAMPING_TX_SOFTWARE)&lt;BR /&gt; hardware-receive (SOF_TIMESTAMPING_RX_HARDWARE)&lt;BR /&gt; software-receive (SOF_TIMESTAMPING_RX_SOFTWARE)&lt;BR /&gt; software-system-clock (SOF_TIMESTAMPING_SOFTWARE)&lt;BR /&gt; hardware-raw-clock (SOF_TIMESTAMPING_RAW_HARDWARE)&lt;BR /&gt;PTP Hardware Clock: 0&lt;BR /&gt;Hardware Transmit Timestamp Modes:&lt;BR /&gt; off (HWTSTAMP_TX_OFF)&lt;BR /&gt; on (HWTSTAMP_TX_ON)&lt;BR /&gt;Hardware Receive Filter Modes:&lt;BR /&gt; none (HWTSTAMP_FILTER_NONE)&lt;BR /&gt; all (HWTSTAMP_FILTER_ALL)&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Below is the slaves output with software time stamp&lt;/P&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;P&gt;root@phyboard-mira-imx6-7:~# ptp4l -i eth0 -S -s -m&lt;BR /&gt;ptp4l[726.639]: port 1: INITIALIZING to LISTENING on INIT_COMPLETE&lt;BR /&gt;ptp4l[726.641]: port 0: INITIALIZING to LISTENING on INIT_COMPLETE&lt;BR /&gt;ptp4l[727.116]: port 1: new foreign master 9840bb.fffe.39baf7-1&lt;BR /&gt;ptp4l[727.118]: port 1: new foreign master 502df4.fffe.0b5840-1&lt;BR /&gt;ptp4l[731.116]: selected best master clock 9840bb.fffe.39baf7&lt;BR /&gt;ptp4l[731.116]: foreign master not using PTP timescale&lt;BR /&gt;ptp4l[731.117]: port 1: LISTENING to UNCALIBRATED on RS_SLAVE&lt;BR /&gt;ptp4l[731.118]: selected best master clock 502df4.fffe.0b5840&lt;BR /&gt;ptp4l[731.118]: foreign master not using PTP timescale&lt;BR /&gt;ptp4l[733.118]: master offset -17883708630450 s0 freq -37532 path delay 59668&lt;BR /&gt;ptp4l[734.118]: master offset -17883708586248 s0 freq -37532 path delay 59668&lt;BR /&gt;ptp4l[735.118]: master offset -17883708545313 s0 freq -37532 path delay 52602&lt;BR /&gt;ptp4l[736.118]: master offset -17883708512346 s0 freq -37532 path delay 55504&lt;BR /&gt;ptp4l[737.118]: master offset -17883708478827 s0 freq -37532 path delay 54187&lt;BR /&gt;ptp4l[738.118]: master offset -17883708445625 s0 freq -37532 path delay 54187&lt;BR /&gt;ptp4l[739.119]: master offset -17883708410979 s0 freq -37532 path delay 56078&lt;BR /&gt;ptp4l[740.119]: master offset -17883708370443 s0 freq -37532 path delay 56078&lt;BR /&gt;ptp4l[741.119]: master offset -17883708350767 s0 freq -37532 path delay 55269&lt;BR /&gt;ptp4l[742.119]: master offset -17883708311806 s0 freq -37532 path delay 55843&lt;BR /&gt;ptp4l[743.119]: master offset -17883708277008 s0 freq -37532 path delay 54246&lt;BR /&gt;ptp4l[744.119]: master offset -17883708233138 s0 freq -37532 path delay 54246&lt;BR /&gt;ptp4l[745.119]: master offset -17883708174601 s0 freq -37532 path delay 54246&lt;BR /&gt;ptp4l[746.119]: master offset -17883708163066 s0 freq -37532 path delay 54246&lt;BR /&gt;ptp4l[747.120]: master offset -17883708118787 s0 freq -37532 path delay 55171&lt;BR /&gt;ptp4l[748.120]: master offset -17883708097060 s0 freq -37532 path delay 56978&lt;BR /&gt;ptp4l[749.120]: master offset -17883708060857 s1 freq -1936 path delay 56978&lt;BR /&gt;ptp4l[750.120]: master offset -5123 s2 freq -2453 path delay 56978&lt;BR /&gt;ptp4l[750.120]: port 1: UNCALIBRATED to SLAVE on MASTER_CLOCK_SELECTED&lt;BR /&gt;ptp4l[751.120]: master offset 993 s2 freq -1841 path delay 56978&lt;BR /&gt;ptp4l[752.120]: master offset -7894 s2 freq -2737 path delay 57711&lt;BR /&gt;ptp4l[753.120]: master offset -6826 s2 freq -2637 path delay 57711&lt;BR /&gt;ptp4l[754.120]: master offset -4274 s2 freq -2386 path delay 58463&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;But with hardware time stamp, i'm not able to sync the clock&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;P&gt;root@phyboard-mira-imx6-7:~# ptp4l -i eth0 -s -m&lt;BR /&gt;ptp4l[1084.333]: selected /dev/ptp0 as PTP clock&lt;BR /&gt;ptp4l[1084.336]: port 1: INITIALIZING to LISTENING on INIT_COMPLETE&lt;BR /&gt;ptp4l[1084.337]: port 0: INITIALIZING to LISTENING on INIT_COMPLETE&lt;BR /&gt;ptp4l[1085.822]: port 1: new foreign master 502df4.fffe.0b5840-1&lt;BR /&gt;ptp4l[1089.823]: selected best master clock 502df4.fffe.0b5840&lt;BR /&gt;ptp4l[1089.823]: port 1: LISTENING to UNCALIBRATED on RS_SLAVE&lt;BR /&gt;ptp4l[1091.822]: master offset -17881927778001 s0 freq +0 path delay 0&lt;BR /&gt;ptp4l[1092.822]: master offset -17881927778001 s0 freq +0 path delay 0&lt;BR /&gt;ptp4l[1093.823]: master offset -17881927778001 s0 freq +0 path delay 0&lt;BR /&gt;ptp4l[1094.823]: master offset -17881927778001 s0 freq +0 path delay 0&lt;BR /&gt;ptp4l[1095.823]: master offset -17881927778001 s0 freq +0 path delay 0&lt;BR /&gt;ptp4l[1096.823]: master offset -17881927778001 s0 freq +0 path delay 0&lt;BR /&gt;ptp4l[1097.823]: master offset -17881927778001 s0 freq +0 path delay 0&lt;BR /&gt;ptp4l[1098.823]: master offset -17881927778001 s0 freq +0 path delay 0&lt;BR /&gt;ptp4l[1099.823]: master offset -17881927778001 s0 freq +0 path delay 0&lt;BR /&gt;ptp4l[1100.823]: master offset -17881927778001 s0 freq +0 path delay 0&lt;BR /&gt;ptp4l[1101.823]: master offset -17881927778001 s0 freq +0 path delay 0&lt;BR /&gt;&lt;BR /&gt;&lt;BR /&gt;&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;Is any additional configurations needed for hardware timestamp?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards&lt;/P&gt;&lt;P&gt;khaleel&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 14 Dec 2018 10:51:17 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Issue-with-ptp-hardware-timestamp-imx6/m-p/800077#M123655</guid>
      <dc:creator>khaleel_s</dc:creator>
      <dc:date>2018-12-14T10:51:17Z</dc:date>
    </item>
    <item>
      <title>Re: Issue with ptp hardware timestamp imx6</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Issue-with-ptp-hardware-timestamp-imx6/m-p/800078#M123656</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I also encountered the same problem, looking forward to the solution&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 27 Aug 2019 08:09:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Issue-with-ptp-hardware-timestamp-imx6/m-p/800078#M123656</guid>
      <dc:creator>pengjing918</dc:creator>
      <dc:date>2019-08-27T08:09:04Z</dc:date>
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