topic Re: imx8m non-cea video modes in i.MX Processors

imx8m non-cea video modes

NeilShipp-MSFT — Tue, 19 Jun 2018 20:00:01 GMT

Is there any better documentation on the HDMI subsystem in the IMX8M devices? I'm attempting to bring up a non-Linux based OS on the device, and am using u-boot as a starting point. The HDMI setup in u-boot seems to be restricted to CEA video standards of 480p, 720p, 1080p, and 2160p and fixed clock frequencies. I'd like to drive computer monitors of 1024x768, 1600x1200, etc. These require different clock rates than phy_cfg_t28hpc() appears to support. Would ungating and setting the video PLL to my required clock rate and calling imx8_hdmi_init with use_phy_pixel_clk set to zero be enough to use other pixel clock rates?

Re: imx8m non-cea video modes

NeilShipp-MSFT — Wed, 20 Jun 2018 22:29:15 GMT

The documentation for DCSS Block Control Control0 seems to be incorrect. In 15.2.2.1.6.4, it says that bit 8 is DISPMIX_PIXCLK_SEL and bits 5-4 are DISPMIX_REFCLK_SEL, but the source code in u-boot for imx8m_power_init() called by video_hw_init() sets the entire register to 0x00000001 to select the clock source which is setting a reserved bit and sets DISPMIX_PIXCLK_SEL to Video PLL2 and DISPMIX_REFCLK_SEL to a 27Mhz oscillator according to the documentation. What is the correct definition for this register?

Re: imx8m non-cea video modes

diegoadrian — Fri, 20 Jul 2018 17:03:01 GMT

Hello,

I apologize for the delay.

> Is there any better documentation on the HDMI subsystem in the IMX8M devices?

Not that I'm aware of.

> Would ungating and setting the video PLL to my required clock rate and calling imx8_hdmi_init with use_phy_pixel_clk set to zero be enough to use other pixel clock rates.

I think it's a good idea, but please keep in mind the hdmi support on u-boot is not complete, it's only a preinitialization for splash screen. For example, I didn't see anything about audio. But I saw it try to figure it out if hdmi is 1.4 or 2.0. Anyway, it's a bootloader, not the driver (I'm only saying the obvious, just in case).

> Regarding the documentation mistake:

There was a change in the DCSS blk_ctl control registers functionality between A0 and B0 silicon to fix reset issues discovered on A0 silicon. The blk_ctl’s CRR register description was updated before the B0 tapeout, but It appears the reference manual has not been updated to reflect this change.

The DCSS designsync tapeout tag for B0 should be used for the documentation update: DA_SSL_DC_SUBSYS_MSCALE8_060

The blk_ctl directory under the dcss design hierarchy is called med_dcss_blk_ctl

For B0 silicon, the blk_ctl’s CONTROL0 register descriptions are as follows:

HDMI_MIPI_CLK_SEL (bit[0])

HDMI or MIPI clock Source Selection

0x0 = MIPI clock source

0x1 = HDMI clock source

DISPMIX_REF_CLK (bits[5:4])

Reference Clock Source Selection

0x0 = 27 MHz Oscillator Reference

0x1 = Video PLL2 Clock

0x2 = CCM DC Pixel Clock

DISPMIX_PIXCLK_SEL (bit[8])

Pixel Clock Source Selection

0x0 = Video PLL Clock

0x1 = CCM DC Pixel Clock

Note: On A0 silicon, the HDMI_MIPI_CLK_SEL (bit[0]) clock sources were reversed:

HDMI_MIPI_CLK_SEL (bit[0])

HDMI or MIPI clock Source Selection

0x0 = HDMI clock source

0x1 = MIPI clock source

Hope this can help you.

Best Regards,

Diego.