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    <title>i.MX ProcessorsのトピックRe: Interrupt Priority</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Interrupt-Priority/m-p/789957#M122443</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;i.MX6 processor uses PL390 Generic Interrupt Controller (GIC).&lt;/P&gt;&lt;P&gt;Here you can get PrimeCell Generic Interrupt Controller(PL390) Technical Reference Manual:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A href="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0416b/DDI0416B_gic_pl390_r0p0_trm.pdf"&gt;http://infocenter.arm.com/help/topic/com.arm.doc.ddi0416b/DDI0416B_gic_pl390_r0p0_trm.pdf&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;You can refer chapter 3.2.9 Priority Level Registers.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Have a great day,&lt;BR /&gt;Victor&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 25 Sep 2018 04:05:37 GMT</pubDate>
    <dc:creator>b36401</dc:creator>
    <dc:date>2018-09-25T04:05:37Z</dc:date>
    <item>
      <title>Interrupt Priority</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Interrupt-Priority/m-p/789956#M122442</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I have an ADC ready shared-interrupt, sharing between gpio-keys and an adc driver.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Once the ADC ready interrupt occurs I would like to execute the gpio-keys ISR first, then the ADC driver ISR.&lt;/P&gt;&lt;P&gt;Currently, it happens vice versa. ie: ADC driver first and GPIO-Keys second. So, I'm facing some timing issues.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;OL&gt;&lt;LI&gt;How to resolve this issue?&lt;/LI&gt;&lt;LI&gt;How to set interrupt priority manually?&lt;/LI&gt;&lt;/OL&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 24 Sep 2018 06:23:36 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Interrupt-Priority/m-p/789956#M122442</guid>
      <dc:creator>mathew_k_t</dc:creator>
      <dc:date>2018-09-24T06:23:36Z</dc:date>
    </item>
    <item>
      <title>Re: Interrupt Priority</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Interrupt-Priority/m-p/789957#M122443</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;i.MX6 processor uses PL390 Generic Interrupt Controller (GIC).&lt;/P&gt;&lt;P&gt;Here you can get PrimeCell Generic Interrupt Controller(PL390) Technical Reference Manual:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;A href="http://infocenter.arm.com/help/topic/com.arm.doc.ddi0416b/DDI0416B_gic_pl390_r0p0_trm.pdf"&gt;http://infocenter.arm.com/help/topic/com.arm.doc.ddi0416b/DDI0416B_gic_pl390_r0p0_trm.pdf&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;You can refer chapter 3.2.9 Priority Level Registers.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Have a great day,&lt;BR /&gt;Victor&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 25 Sep 2018 04:05:37 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Interrupt-Priority/m-p/789957#M122443</guid>
      <dc:creator>b36401</dc:creator>
      <dc:date>2018-09-25T04:05:37Z</dc:date>
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