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    <title>i.MX ProcessorsのトピックRe: iMX8 CSI documentation</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/iMX8-CSI-documentation/m-p/789492#M122355</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I have this issue too, trying to find out what's wrong in my MIPI CSI, but cannot understand what is doing in mxc-mipi-csi2_yav and mx6s_capture in existing document ~"~&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 11 Sep 2018 03:40:30 GMT</pubDate>
    <dc:creator>michaeltang</dc:creator>
    <dc:date>2018-09-11T03:40:30Z</dc:date>
    <item>
      <title>iMX8 CSI documentation</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX8-CSI-documentation/m-p/789489#M122352</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;where can I find documentation about the iMX8 CSI controller?&amp;nbsp; The available reference manual rev.0 lists three address ranges per controller:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_1.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/68066iC78386A185E927AA/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_1.png" alt="pastedImage_1.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;But there is only a "MIPI CS Host Controller (MIPI_CS)" chapter which seems to cover only one of these three ranges.:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_2.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/68021i2CAEC06DD83BE000/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_2.png" alt="pastedImage_2.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;What is this base address 100h?&amp;nbsp; Where are the other units described?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Tnanks&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 04 Sep 2018 14:06:41 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX8-CSI-documentation/m-p/789489#M122352</guid>
      <dc:creator>ensc</dc:creator>
      <dc:date>2018-09-04T14:06:41Z</dc:date>
    </item>
    <item>
      <title>Re: iMX8 CSI documentation</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX8-CSI-documentation/m-p/789490#M122353</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;First, most likely, you mean the i.MX8M family of processors, since the i.MX8 and i.MX8X families are not released yet.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;So, the i.MX8M series processors have 2 MIPI_CSI camera interfaces of four lanes each. So, all references to the CSI (not MIPI_CSI) interfaces should be treated as "Reserved" in the Memory Map and Interrupt map descriptions. Also, there is nothing to access by application software in the MIPI_CSI_PHY modules, so, the corresponding address ranges also should be treated as "Reserved".&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Also, the "Base Address 100h" in the MIPI_CSI register descriptions section is just a typo, just ignore it. The actual base addresses of each of two MIPI_CSI modules are listed in the Memory Map table.&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Artur&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 06 Sep 2018 11:13:31 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX8-CSI-documentation/m-p/789490#M122353</guid>
      <dc:creator>art</dc:creator>
      <dc:date>2018-09-06T11:13:31Z</dc:date>
    </item>
    <item>
      <title>Re: iMX8 CSI documentation</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX8-CSI-documentation/m-p/789491#M122354</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;P&gt;First, most likely, you mean the i.MX8M family of processors&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;yes; I tried to set the corresponding "category" but this does not seem to work (HTTP server returns a "404 not fond").&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;P&gt;So, all references to the CSI (not MIPI_CSI) interfaces should be treated as "Reserved" in the Memory Map and Interrupt map descriptions&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;The Linux BSP uses the mx6s_capture.c driver to access the csi1_bridge@30a90000 range so this range does not seem to be "reserved" and can be accessed by applications.&amp;nbsp;&amp;nbsp; But where can I find documentation about this "CSI1" (30a90000) range?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;0x30a70000 (which is used by the mxc-mipi-csi2_yav.c driver) seems to setup some physical parameters but documentation does not contain any information e.g. where to setup addresses used for DMA or where EOF interrupts can be enabled.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;There is some reference to a (misspelled)&amp;nbsp; "CSI-2 Controller User Guice"; where can I find this document?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 06 Sep 2018 12:35:30 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX8-CSI-documentation/m-p/789491#M122354</guid>
      <dc:creator>ensc</dc:creator>
      <dc:date>2018-09-06T12:35:30Z</dc:date>
    </item>
    <item>
      <title>Re: iMX8 CSI documentation</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX8-CSI-documentation/m-p/789492#M122355</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I have this issue too, trying to find out what's wrong in my MIPI CSI, but cannot understand what is doing in mxc-mipi-csi2_yav and mx6s_capture in existing document ~"~&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 11 Sep 2018 03:40:30 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX8-CSI-documentation/m-p/789492#M122355</guid>
      <dc:creator>michaeltang</dc:creator>
      <dc:date>2018-09-11T03:40:30Z</dc:date>
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