topic Re: i.MX6 IPU memory map address in i.MX Processors

i.MX6 IPU memory map address

zandar — Fri, 15 Jun 2018 12:21:18 GMT

Hi,

I would like to ask what are the correct addresses of the IPU block in i.MX6S/DL/Q SoCs.

There is a difference in what the TRM says - System memory map:

Start address | End address | Size | Description
02A0_0000 | 02DF_FFFF | 4 MB | IPU-2
0260_0000 | 029F_FFFF | 4 MB | IPU-1

and what addresses are used in device trees:

                ipu1: ipu@02400000 {
                        #address-cells = <1>;
                        #size-cells = <0>;
                        compatible = "fsl,imx6q-ipu";
                        reg = <0x02400000 0x400000>;
                ipu2: ipu@02800000 {
                        #address-cells = <1>;
                        #size-cells = <0>;
                        compatible = "fsl,imx6q-ipu";
                        reg = <0x02800000 0x400000>;

All other addresses are correct. The ones from TRM match with those from device tree.

Is this a bug in the device trees? Or in the TRM? Or some maggic is happaning in background?

Thanks,

Michal

Re: i.MX6 IPU memory map address

igorpadykov — Fri, 15 Jun 2018 23:36:27 GMT

Hi Michal

device trees values are correct (also one can check mx6.h), seems this is misprint in Reference Manual.

Best regards
igor
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Re: i.MX6 IPU memory map address

zandar — Mon, 18 Jun 2018 07:42:45 GMT

OK, thank you Igor.

It is weird that it was not caught earlier. I found the wrong values in all three datasheet revisions for both the Solo/DualLite and Quad SoC.

Thanks again,

Michal

Re: i.MX6 IPU memory map address

jotes — Thu, 12 Jul 2018 12:58:28 GMT

I'm not an expert, but I quess 0x2600000 and 0x2A00000 are the correct addresses.

https://community.nxp.com/thread/315255#comment-361222