topic Re: IMX6UL Boot ROM IOMUX configuration in i.MX Processors

IMX6UL Boot ROM IOMUX configuration

christopheniclaes — Tue, 11 Dec 2018 09:22:10 GMT

I've a new custom board with IMX6UL configured to boot on USDHC1 controller with an eMMC connected.

I can't find a document describing what's the IOMUX configuration used by the ROM Bootloader when it starts, in order for me to be sure that the way I connected some signals is correct.

My specific problem is related to the nRST signal of the eMMC which is connected to NAND_WP_B (which has the USDHC1_RESET_B function available). What I/O is used by the ROM Bootloader for this function?

Do you have a document describing the complete I/O mapping used by the ROM Bootloader?

Re: IMX6UL Boot ROM IOMUX configuration

igorpadykov — Wed, 12 Dec 2018 00:08:54 GMT

Hi Christophe

I/O mapping can be found in Table 8-18. SD/MMC IOMUX Pin Configuration

i.MX6UL Reference Manual

http://www.nxp.com/docs/en/reference-manual/IMX6ULRM.pdf

Best regards
igor
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Re: IMX6UL Boot ROM IOMUX configuration

christopheniclaes — Wed, 12 Dec 2018 06:52:35 GMT

Thank you! I missed this table in the Reference Manual!