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    <title>i.MX ProcessorsのトピックHow enable cache on PCIe in i.MX6?</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/How-enable-cache-on-PCIe-in-i-MX6/m-p/783313#M121553</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P style="margin: 0mm 0mm 0.0001pt; font-size: 10.5pt; color: #000000; font-weight: 400; text-indent: 0px;"&gt;Dear All,&lt;/P&gt;&lt;P style="margin: 0mm 0mm 0.0001pt; font-size: 10.5pt; color: #000000; font-weight: 400; text-indent: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P style="margin: 0mm 0mm 0.0001pt; font-size: 10.5pt; color: #000000; font-weight: 400; text-indent: 0px;"&gt;I am using i.MX6 as PCIe RC. I will write data via PCIe to EP device by ARM CPU.&lt;/P&gt;&lt;P style="margin: 0mm 0mm 0.0001pt; font-size: 10.5pt; color: #000000; font-weight: 400; text-indent: 0px;"&gt;I want to write with as much as possible large TLP packet by ARM CPU in i.MX6, but I can only 8 byte with memcpy() in yocto linux.&lt;/P&gt;&lt;P style="margin: 0mm 0mm 0.0001pt; font-size: 10.5pt; color: #000000; font-weight: 400; text-indent: 0px;"&gt;I referred the community, I found that i.MX6 can write by 32 byte unit at PCIe cached.&lt;/P&gt;&lt;P style="margin: 0mm 0mm 0.0001pt; font-size: 10.5pt; color: #000000; font-weight: 400; text-indent: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P style="margin: 0mm 0mm 0.0001pt; font-size: 10.5pt; color: #000000; font-weight: 400; text-indent: 0px;"&gt;I referred to patch code attached to&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;A _jive_internal="true" href="https://community.nxp.com/docs/DOC-95014" style="color: #954f72; text-decoration: underline;"&gt;https://community.nxp.com/docs/DOC-95014&lt;/A&gt;.&lt;/P&gt;&lt;P style="margin: 0mm 0mm 0.0001pt; font-size: 10.5pt; color: #000000; font-weight: 400; text-indent: 0px;"&gt;I thought it will be ok that I modify pci-imx6.c , but this patch had many different from my driver. And, I thought many codes of modification of its patch was for EP side. &amp;nbsp;&lt;/P&gt;&lt;P style="margin: 0mm 0mm 0.0001pt; font-size: 10.5pt; color: #000000; font-weight: 400; text-indent: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P style="margin: 0mm 0mm 0.0001pt; font-size: 10.5pt; color: #000000; font-weight: 400; text-indent: 0px;"&gt;Please tell me, how can I enable cache on PCIe? If cache is enable, then can I write over 8 bytes unit TLP packet from ARM CPU in RC side i.MX6?&lt;/P&gt;&lt;P style="margin: 0mm 0mm 0.0001pt; font-size: 10.5pt; color: #000000; font-weight: 400; text-indent: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P style="margin: 0mm 0mm 0.0001pt; font-size: 10.5pt; color: #000000; font-weight: 400; text-indent: 0px;"&gt;And, if I use PCIe with cached, is that system able to use stable?&lt;/P&gt;&lt;P style="margin: 0mm 0mm 0.0001pt; font-size: 10.5pt; color: #000000; font-weight: 400; text-indent: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P style="margin: 0mm 0mm 0.0001pt; font-size: 10.5pt; color: #000000; font-weight: 400; text-indent: 0px;"&gt;Best Regards,&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Sun, 02 Sep 2018 10:36:42 GMT</pubDate>
    <dc:creator>massohy</dc:creator>
    <dc:date>2018-09-02T10:36:42Z</dc:date>
    <item>
      <title>How enable cache on PCIe in i.MX6?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/How-enable-cache-on-PCIe-in-i-MX6/m-p/783313#M121553</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P style="margin: 0mm 0mm 0.0001pt; font-size: 10.5pt; color: #000000; font-weight: 400; text-indent: 0px;"&gt;Dear All,&lt;/P&gt;&lt;P style="margin: 0mm 0mm 0.0001pt; font-size: 10.5pt; color: #000000; font-weight: 400; text-indent: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P style="margin: 0mm 0mm 0.0001pt; font-size: 10.5pt; color: #000000; font-weight: 400; text-indent: 0px;"&gt;I am using i.MX6 as PCIe RC. I will write data via PCIe to EP device by ARM CPU.&lt;/P&gt;&lt;P style="margin: 0mm 0mm 0.0001pt; font-size: 10.5pt; color: #000000; font-weight: 400; text-indent: 0px;"&gt;I want to write with as much as possible large TLP packet by ARM CPU in i.MX6, but I can only 8 byte with memcpy() in yocto linux.&lt;/P&gt;&lt;P style="margin: 0mm 0mm 0.0001pt; font-size: 10.5pt; color: #000000; font-weight: 400; text-indent: 0px;"&gt;I referred the community, I found that i.MX6 can write by 32 byte unit at PCIe cached.&lt;/P&gt;&lt;P style="margin: 0mm 0mm 0.0001pt; font-size: 10.5pt; color: #000000; font-weight: 400; text-indent: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P style="margin: 0mm 0mm 0.0001pt; font-size: 10.5pt; color: #000000; font-weight: 400; text-indent: 0px;"&gt;I referred to patch code attached to&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;A _jive_internal="true" href="https://community.nxp.com/docs/DOC-95014" style="color: #954f72; text-decoration: underline;"&gt;https://community.nxp.com/docs/DOC-95014&lt;/A&gt;.&lt;/P&gt;&lt;P style="margin: 0mm 0mm 0.0001pt; font-size: 10.5pt; color: #000000; font-weight: 400; text-indent: 0px;"&gt;I thought it will be ok that I modify pci-imx6.c , but this patch had many different from my driver. And, I thought many codes of modification of its patch was for EP side. &amp;nbsp;&lt;/P&gt;&lt;P style="margin: 0mm 0mm 0.0001pt; font-size: 10.5pt; color: #000000; font-weight: 400; text-indent: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P style="margin: 0mm 0mm 0.0001pt; font-size: 10.5pt; color: #000000; font-weight: 400; text-indent: 0px;"&gt;Please tell me, how can I enable cache on PCIe? If cache is enable, then can I write over 8 bytes unit TLP packet from ARM CPU in RC side i.MX6?&lt;/P&gt;&lt;P style="margin: 0mm 0mm 0.0001pt; font-size: 10.5pt; color: #000000; font-weight: 400; text-indent: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P style="margin: 0mm 0mm 0.0001pt; font-size: 10.5pt; color: #000000; font-weight: 400; text-indent: 0px;"&gt;And, if I use PCIe with cached, is that system able to use stable?&lt;/P&gt;&lt;P style="margin: 0mm 0mm 0.0001pt; font-size: 10.5pt; color: #000000; font-weight: 400; text-indent: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P style="margin: 0mm 0mm 0.0001pt; font-size: 10.5pt; color: #000000; font-weight: 400; text-indent: 0px;"&gt;Best Regards,&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sun, 02 Sep 2018 10:36:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/How-enable-cache-on-PCIe-in-i-MX6/m-p/783313#M121553</guid>
      <dc:creator>massohy</dc:creator>
      <dc:date>2018-09-02T10:36:42Z</dc:date>
    </item>
    <item>
      <title>Re: How enable cache on PCIe in i.MX6?</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/How-enable-cache-on-PCIe-in-i-MX6/m-p/783314#M121554</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi mas&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;below link provides solution for improving pcie performance using arm core (with cache enabled) or ipu&lt;/P&gt;&lt;P&gt;dma as masters for RC side. I am afraid there are no other ways to improve it.&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/docs/DOC-95014"&gt;i.MX6Q PCIe EP/RC Validation System&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 03 Sep 2018 09:46:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/How-enable-cache-on-PCIe-in-i-MX6/m-p/783314#M121554</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2018-09-03T09:46:26Z</dc:date>
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