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    <title>i.MX ProcessorsのトピックFLEXCAN register vs. Supervisor-User-Secure-Non-Secure</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/FLEXCAN-register-vs-Supervisor-User-Secure-Non-Secure/m-p/780460#M121261</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi all, pls, I'm working on an iMX6Q platform and when I try to read the FLEXCAN memory map (the MCR register&amp;nbsp; 209_0000 instead the CTRL register 209_0004...) the system generate an exception. From what I read in datasheet "&lt;EM&gt;The access type can be Supervisor (S) or Unrestricted (U).&amp;nbsp;Most of the registers can be configured to have either Supervisor or Unrestricted access&amp;nbsp;by programming the SUPV bit in the MCR Register. The MCR register allows only&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Supervisor access regardless the SUPV bit state&lt;/EM&gt;" therefore I need to switch in Supervisor Secure Mode by the&amp;nbsp;CSU_CSLx registers. There registers control teh access for each peripheral.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;for additional clarification also in the FLEXCAN chapter is wroten "&lt;EM&gt;SUPV bit configures some of the FLEXCAN registers to be either in Supervisor or User Mode. Reset value&amp;nbsp;of this bit is '1', so the affected registers start with Supervisor access allowance only. This bit can only be&amp;nbsp;written in Freeze mode as it is blocked by hardware in other modes.&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;1 FlexCAN is in Supervisor Mode. Affected registers allow only Supervisor access. &lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM&gt;!!!! Unrestricted access&amp;nbsp;&lt;/EM&gt;&lt;EM&gt;behaves as though the access was done to an unimplemented register location !!!!&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;0 FlexCAN is in User Mode. Affected registers allow both Supervisor and Unrestricted accesses&lt;/EM&gt;"&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Currently the CSU_CSL0 at 021c:0000 and CSU_CSL1 at 021c:0004 are 00330033 that means Supervisor and User Secure Only while I need to force them at 00FF0033 and 003300FF respectively.&lt;/P&gt;&lt;P&gt;I need to find the sentences to punt in the Device Tree customization ... DTB&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Does anybody pls hepl me in that item?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Tks for all your time and attention.&lt;/P&gt;&lt;P&gt;Best Regards, Davide&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 11 Jan 2018 12:06:44 GMT</pubDate>
    <dc:creator>davideponzetti</dc:creator>
    <dc:date>2018-01-11T12:06:44Z</dc:date>
    <item>
      <title>FLEXCAN register vs. Supervisor-User-Secure-Non-Secure</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/FLEXCAN-register-vs-Supervisor-User-Secure-Non-Secure/m-p/780460#M121261</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi all, pls, I'm working on an iMX6Q platform and when I try to read the FLEXCAN memory map (the MCR register&amp;nbsp; 209_0000 instead the CTRL register 209_0004...) the system generate an exception. From what I read in datasheet "&lt;EM&gt;The access type can be Supervisor (S) or Unrestricted (U).&amp;nbsp;Most of the registers can be configured to have either Supervisor or Unrestricted access&amp;nbsp;by programming the SUPV bit in the MCR Register. The MCR register allows only&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;Supervisor access regardless the SUPV bit state&lt;/EM&gt;" therefore I need to switch in Supervisor Secure Mode by the&amp;nbsp;CSU_CSLx registers. There registers control teh access for each peripheral.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;for additional clarification also in the FLEXCAN chapter is wroten "&lt;EM&gt;SUPV bit configures some of the FLEXCAN registers to be either in Supervisor or User Mode. Reset value&amp;nbsp;of this bit is '1', so the affected registers start with Supervisor access allowance only. This bit can only be&amp;nbsp;written in Freeze mode as it is blocked by hardware in other modes.&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;1 FlexCAN is in Supervisor Mode. Affected registers allow only Supervisor access. &lt;/EM&gt;&lt;/P&gt;&lt;P&gt;&lt;EM&gt;!!!! Unrestricted access&amp;nbsp;&lt;/EM&gt;&lt;EM&gt;behaves as though the access was done to an unimplemented register location !!!!&lt;/EM&gt;&lt;BR /&gt;&lt;EM&gt;0 FlexCAN is in User Mode. Affected registers allow both Supervisor and Unrestricted accesses&lt;/EM&gt;"&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Currently the CSU_CSL0 at 021c:0000 and CSU_CSL1 at 021c:0004 are 00330033 that means Supervisor and User Secure Only while I need to force them at 00FF0033 and 003300FF respectively.&lt;/P&gt;&lt;P&gt;I need to find the sentences to punt in the Device Tree customization ... DTB&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Does anybody pls hepl me in that item?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Tks for all your time and attention.&lt;/P&gt;&lt;P&gt;Best Regards, Davide&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 11 Jan 2018 12:06:44 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/FLEXCAN-register-vs-Supervisor-User-Secure-Non-Secure/m-p/780460#M121261</guid>
      <dc:creator>davideponzetti</dc:creator>
      <dc:date>2018-01-11T12:06:44Z</dc:date>
    </item>
    <item>
      <title>Re: FLEXCAN register vs. Supervisor-User-Secure-Non-Secure</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/FLEXCAN-register-vs-Supervisor-User-Secure-Non-Secure/m-p/780461#M121262</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Davide&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;for accessing registers one can try memtool :&lt;/P&gt;&lt;P&gt;imx-test (./test/memtool)&lt;BR /&gt;&lt;A href="http://www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-test-5.7.tar.gz"&gt;www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-test-5.7.tar.gz&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/thread/388442"&gt;https://community.nxp.com/thread/388442&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 11 Jan 2018 23:14:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/FLEXCAN-register-vs-Supervisor-User-Secure-Non-Secure/m-p/780461#M121262</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2018-01-11T23:14:48Z</dc:date>
    </item>
    <item>
      <title>Re: FLEXCAN register vs. Supervisor-User-Secure-Non-Secure</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/FLEXCAN-register-vs-Supervisor-User-Secure-Non-Secure/m-p/780462#M121263</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Pls do you know how can I access to the link below? tks&lt;/P&gt;&lt;UL style="color: #51626f; background-color: #ffffff; border: 0px; padding: 0px 0px 0px 30px;"&gt;&lt;LI style="border: 0px; font-weight: inherit; margin: 0.5ex 0px;"&gt;&lt;SPAN lang="EN-US" style="border: 0px; font-weight: inherit;"&gt;&lt;A class="" data-containerid="8016" data-containertype="2020" data-content-finding="Community" data-objectid="94887" data-objecttype="102" href="https://community.freescale.com/docs/DOC-94887" style="color: #5e89c1; background-color: transparent; border: 0px; font-weight: inherit; padding: 1px 0px 1px calc(12px + 0.35ex);"&gt;https://community.freescale.com/docs/DOC-94887&lt;/A&gt;&lt;/SPAN&gt;&lt;SPAN lang="EN-US" style="border: 0px; font-weight: inherit;"&gt;&lt;/SPAN&gt;&lt;/LI&gt;&lt;/UL&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 18 Jan 2018 15:56:44 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/FLEXCAN-register-vs-Supervisor-User-Secure-Non-Secure/m-p/780462#M121263</guid>
      <dc:creator>davideponzetti</dc:creator>
      <dc:date>2018-01-18T15:56:44Z</dc:date>
    </item>
    <item>
      <title>Re: FLEXCAN register vs. Supervisor-User-Secure-Non-Secure</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/FLEXCAN-register-vs-Supervisor-User-Secure-Non-Secure/m-p/780463#M121264</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;this is private thread with restricted access. May be you can&lt;/P&gt;&lt;P&gt;try to get help with access from local nxp marketing office.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 18 Jan 2018 23:22:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/FLEXCAN-register-vs-Supervisor-User-Secure-Non-Secure/m-p/780463#M121264</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2018-01-18T23:22:20Z</dc:date>
    </item>
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