Parallel CSI interface is not working for me

jirislaby — Thu, 01 Feb 2018 14:02:54 GMT

Hi,

I have an IMX.6 board and I am trying to make the CSI parallel interface working. I want to transfer generic 16-bit data from FPGA via gated clock mode. Connected are DATA04..DATA19, VSYNC, HSYNC, PIXCLK (75 MHz). DATA_EN is not connected.

MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x0001b0b0
MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x0001b0b0
MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x0001b0b0
MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x0001b0b0
MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x0001b0b0
MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x0001b0b0
MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x0001b0b0
MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x0001b0b0
MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x0001b0b0
MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x0001b0b0
MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x0001b0b0
MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x0001b0b0
MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x0001b0b0
MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x0001b0b0
MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x0001b0b0
MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x0001b0b0
MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x0001b0b0

VSYNC is put high and down
HSYNC is put high
data for a line are put on DATA[04..19]
HSYNC is put down

PIXCLK ticks all the time

The line is 280B of blanking and 1920 B of data.

The frames are 41 lines of blanking, 1080 active lines and 3 lines of blanking.

The registers are as follows:

[ 93.079402] wwp2 wwp2.24: IOMUXC_GPR1=48693005
[ 93.084458] wwp2 wwp2.24: wwp2 sensor probed !
[ 93.091935] imx-ipuv3 2400000.ipu: clk_mode=0
[ 93.119724] imx-ipuv3 2400000.ipu: init channel = 15
[ 93.119745] imx-ipuv3 2400000.ipu: ipu busfreq high requst.
[ 93.119773] imx-ipuv3 2400000.ipu: initializing idma ch 0 @ c0900000
[ 93.119797] imx-ipuv3 2400000.ipu: ch 0 word 0 - 00000000 00000000 00000000 E0001800 0010DCEF
[ 93.119811] imx-ipuv3 2400000.ipu: ch 0 word 1 - 08860000 0111C000 00C7C000 0003BFC0 00000000
[ 93.119820] imx-ipuv3 2400000.ipu: PFS 0x6,
[ 93.119828] imx-ipuv3 2400000.ipu: BPP 0x3,
[ 93.119835] imx-ipuv3 2400000.ipu: NPB 0x1f
[ 93.119844] imx-ipuv3 2400000.ipu: FW 1919,
[ 93.119852] imx-ipuv3 2400000.ipu: FH 1079,
[ 93.119859] imx-ipuv3 2400000.ipu: EBA0 0x44300000
[ 93.119868] imx-ipuv3 2400000.ipu: EBA1 0x44700000
[ 93.119876] imx-ipuv3 2400000.ipu: Stride 3839
[ 93.119883] imx-ipuv3 2400000.ipu: scan_order 0
[ 93.119890] imx-ipuv3 2400000.ipu: uv_stride 0
[ 93.119898] imx-ipuv3 2400000.ipu: u_offset 0x0
[ 93.119907] imx-ipuv3 2400000.ipu: v_offset 0x0
[ 93.119914] imx-ipuv3 2400000.ipu: Width0 0+1,
[ 93.119921] imx-ipuv3 2400000.ipu: Width1 0+1,
[ 93.119928] imx-ipuv3 2400000.ipu: Width2 0+1,
[ 93.119935] imx-ipuv3 2400000.ipu: Width3 0+1,
[ 93.119942] imx-ipuv3 2400000.ipu: Offset0 0,
[ 93.119949] imx-ipuv3 2400000.ipu: Offset1 0,
[ 93.119957] imx-ipuv3 2400000.ipu: Offset2 0,
[ 93.119963] imx-ipuv3 2400000.ipu: Offset3 0
[ 93.119982] -------
[ 93.122092] imx-ipuv3 2400000.ipu: CSI_SENS_CONF: 0402cb00
[ 93.122100] imx-ipuv3 2400000.ipu: CSI_SENS_FRM_SIZE: 04640897
[ 93.122109] imx-ipuv3 2400000.ipu: CSI_ACT_FRM_SIZE: 0437077f
[ 93.122117] imx-ipuv3 2400000.ipu: CSI_OUT_FRM_CTRL: 01180000
[ 93.122125] imx-ipuv3 2400000.ipu: CSI_TST_CTRL: 00000000
[ 93.122133] imx-ipuv3 2400000.ipu: CSI_CCIR_CODE_1: 00000000
[ 93.122142] imx-ipuv3 2400000.ipu: CSI_CCIR_CODE_2: 00000000
[ 93.122149] imx-ipuv3 2400000.ipu: CSI_CCIR_CODE_3: 00000000
[ 93.122156] imx-ipuv3 2400000.ipu: CSI_MIPI_DI: ffffffff
[ 93.122164] imx-ipuv3 2400000.ipu: CSI_SKIP: 00000000
[ 93.122173] imx-ipuv3 2400000.ipu: SMFC_MAP: 00000000
[ 93.122184] imx-ipuv3 2400000.ipu: IPU_freq = 264000000
[ 93.122192] imx-ipuv3 2400000.ipu: IPU_CONF = 0x00000101
[ 93.122200] imx-ipuv3 2400000.ipu: IDMAC_CONF = 0x0000002F
[ 93.122209] imx-ipuv3 2400000.ipu: IDMAC_CHA_EN1 = 0x00000001
[ 93.122218] imx-ipuv3 2400000.ipu: IDMAC_CHA_EN2 = 0x00000000
[ 93.122227] imx-ipuv3 2400000.ipu: IDMAC_CHA_PRI1 = 0x18800003
[ 93.122235] imx-ipuv3 2400000.ipu: IDMAC_CHA_PRI2 = 0x00000000
[ 93.122242] imx-ipuv3 2400000.ipu: IDMAC_BAND_EN1 = 0x00000000
[ 93.122250] imx-ipuv3 2400000.ipu: IDMAC_BAND_EN2 = 0x00000000
[ 93.122258] imx-ipuv3 2400000.ipu: IPU_CHA_DB_MODE_SEL0 = 0x00000001
[ 93.122267] imx-ipuv3 2400000.ipu: IPU_CHA_DB_MODE_SEL1 = 0x00000000
[ 93.122276] imx-ipuv3 2400000.ipu: IPU_CHA_TRB_MODE_SEL0 = 0x00000000
[ 93.122285] imx-ipuv3 2400000.ipu: IPU_CHA_TRB_MODE_SEL1 = 0x00000000
[ 93.122294] imx-ipuv3 2400000.ipu: DMFC_WR_CHAN = 0x00000090
[ 93.122302] imx-ipuv3 2400000.ipu: DMFC_WR_CHAN_DEF = 0x202020F6
[ 93.122309] imx-ipuv3 2400000.ipu: DMFC_DP_CHAN = 0x00009694
[ 93.122317] imx-ipuv3 2400000.ipu: DMFC_DP_CHAN_DEF = 0x2020F6F6
[ 93.122325] imx-ipuv3 2400000.ipu: DMFC_IC_CTRL = 0x00000002
[ 93.122332] imx-ipuv3 2400000.ipu: IPU_FS_PROC_FLOW1 = 0x00000000
[ 93.122340] imx-ipuv3 2400000.ipu: IPU_FS_PROC_FLOW2 = 0x00000000
[ 93.122349] imx-ipuv3 2400000.ipu: IPU_FS_PROC_FLOW3 = 0x00000000
[ 93.122357] imx-ipuv3 2400000.ipu: IPU_FS_DISP_FLOW1 = 0x00000000
[ 93.122366] imx-ipuv3 2400000.ipu: IPU_VDIC_VDI_FSIZE = 0x00000000
[ 93.122373] imx-ipuv3 2400000.ipu: IPU_VDIC_VDI_C = 0x00000000
[ 93.122382] imx-ipuv3 2400000.ipu: IPU_IC_CONF = 0x00000000
[ 93.122392] imx-ipuv3 2400000.ipu: IDMAC_CH_BUSY = 0x00000000
[ 93.133646] imx-ipuv3 2400000.ipu: IDMAC_CH_BUSY = 0x00000000

I can get data when I setup the CSI testing mode (which is 8bit). But not via the parallel interface:

I get no end of frame interrupts
I get no data
IDMAC channel is never busy (opposing to CSI testing mode)

Can somebody see anything wrong in the above? Or maybe the signals from the FPGA are not correct?

/proc/cpuinfo shows:

Hardware : Freescale i.MX6 Quad/DualLite (Device Tree)

The board is APF6 from Armadeus.

Thanks.

Re: Parallel CSI interface is not working for me

igorpadykov — Thu, 01 Feb 2018 23:26:26 GMT

Hi Jiri

for data_en one can pull-up it internally and select necessary

settings with IPUx_CSI0_SENS_CONF bit CSI0_DATA_EN_POL

and try to test with unit test:

imx-test
www.nxp.com/lgfiles/NMG/MAD/YOCTO/imx-test-5.7.tar.gz

or baremetal sdk:

Github SDK
https://github.com/backenklee/swp-report/tree/master/iMX6_Platform_SDK

Best regards
igor
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Re: Parallel CSI interface is not working for me

jirislaby — Fri, 02 Feb 2018 18:54:10 GMT

Thanks Igor,

So I tried to wire data_en in FPGA to be always on the level 1 (I also tried to switch data_en_pol in CSI_SENS_CONF), but there is no difference :smileysad:. The data on the oscilloscope look sensible though. So I tried to switch all the inputs on the IOMUX to GPIOs and tried to grab the values in a loop:

[ 680.327023] GPIOs: KEY=1 GPIO5=11110101010001 GPIO6=111101
[ 680.332819] GPIOs: KEY=1 GPIO5=11111111000000 GPIO6=000000
[ 680.338631] GPIOs: KEY=1 GPIO5=10110001000000 GPIO6=000011
[ 680.344448] GPIOs: KEY=1 GPIO5=10110011110010 GPIO6=011000
[ 680.350244] GPIOs: KEY=1 GPIO5=10111001110000 GPIO6=100000
[ 680.356056] GPIOs: KEY=1 GPIO5=11110001010000 GPIO6=000000
[ 680.361851] GPIOs: KEY=1 GPIO5=11110001001010 GPIO6=100111
[ 680.367661] GPIOs: KEY=1 GPIO5=11110001010010 GPIO6=111111
[ 680.373459] GPIOs: KEY=1 GPIO5=11111011001010 GPIO6=110000
[ 680.379269] GPIOs: KEY=1 GPIO5=10111101100110 GPIO6=100000
...

This only worked after I changed the dts pin configs from 0x1b0b0 to 0xb0b1:

MX6QDL_PAD_CSI0_PIXCLK__GPIO5_IO18 0xb0b1
MX6QDL_PAD_CSI0_MCLK__GPIO5_IO19 0xb0b1
MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0xb0b1
MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21 0xb0b1

What is suspicious is that VSYNC and PIXCLK never changes. Are the pin configs correct for ~ 75 MHz?

I am not sure how the tests would help me when there are no data coming to the CSI?

Re: Parallel CSI interface is not working for me

jirislaby — Fri, 09 Feb 2018 07:07:07 GMT

So it turned out to be a HW problem. The PIXCLK and VSYNC pins were grounded due to improper soldering.

After fixing this, DATA_EN indeed has to be in logic 1 to have this beast working.

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