<?xml version="1.0" encoding="UTF-8"?>
<rss xmlns:content="http://purl.org/rss/1.0/modules/content/" xmlns:dc="http://purl.org/dc/elements/1.1/" xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:taxo="http://purl.org/rss/1.0/modules/taxonomy/" version="2.0">
  <channel>
    <title>i.MX Processors中的主题 iMX6 SPI Question</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/iMX6-SPI-Question/m-p/778773#M120979</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;I’m newbie to the embedded world and firmware development. Please excuse me for questions. I’m using iMX6 SOM for my project and one of the requirements for the project is to use SPI in master mode with SPI_RDY. I want SPI Data Ready Control to be level-triggered. Could someone clarify my questions:&lt;/P&gt;&lt;OL&gt;&lt;LI style="text-indent: -.25in;"&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; How can I set ECSPI_CONREG[DRCTL] bit from user space?&lt;/LI&gt;&lt;LI style="text-indent: -.25in;"&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;I want SPIDEV test application to wait for spi_ready signal and not to timeout (transfer timeout errors). How can I disable or increase the timeout during development testing?&lt;/LI&gt;&lt;/OL&gt;&lt;P style="margin-bottom: .0001pt;"&gt;Thanks,&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;Chaithu&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 15 Nov 2017 16:32:40 GMT</pubDate>
    <dc:creator>chaithucheruku</dc:creator>
    <dc:date>2017-11-15T16:32:40Z</dc:date>
    <item>
      <title>iMX6 SPI Question</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX6-SPI-Question/m-p/778773#M120979</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;I’m newbie to the embedded world and firmware development. Please excuse me for questions. I’m using iMX6 SOM for my project and one of the requirements for the project is to use SPI in master mode with SPI_RDY. I want SPI Data Ready Control to be level-triggered. Could someone clarify my questions:&lt;/P&gt;&lt;OL&gt;&lt;LI style="text-indent: -.25in;"&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; How can I set ECSPI_CONREG[DRCTL] bit from user space?&lt;/LI&gt;&lt;LI style="text-indent: -.25in;"&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp;I want SPIDEV test application to wait for spi_ready signal and not to timeout (transfer timeout errors). How can I disable or increase the timeout during development testing?&lt;/LI&gt;&lt;/OL&gt;&lt;P style="margin-bottom: .0001pt;"&gt;Thanks,&lt;/P&gt;&lt;P style="margin-bottom: .0001pt;"&gt;Chaithu&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Nov 2017 16:32:40 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX6-SPI-Question/m-p/778773#M120979</guid>
      <dc:creator>chaithucheruku</dc:creator>
      <dc:date>2017-11-15T16:32:40Z</dc:date>
    </item>
    <item>
      <title>Re: iMX6 SPI Question</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX6-SPI-Question/m-p/778774#M120980</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I think you can try to control the spi driver by using ioctl. you can take the spidev.c and spidev.h for reference.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 28 Nov 2017 03:24:55 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX6-SPI-Question/m-p/778774#M120980</guid>
      <dc:creator>jimmychan</dc:creator>
      <dc:date>2017-11-28T03:24:55Z</dc:date>
    </item>
    <item>
      <title>Re: iMX6 SPI Question</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/iMX6-SPI-Question/m-p/778775#M120981</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Please excuse me for silly questions, can I read and write&amp;nbsp;&lt;SPAN style="color: #51626f; background-color: #ffffff; text-indent: -24px;"&gt;ECSPI_CONREG[DRCTL] bit&lt;SPAN&gt;&amp;nbsp;using&lt;/SPAN&gt;&lt;/SPAN&gt;&amp;nbsp;SPI_IOC_RD_MODE32&amp;nbsp; and&amp;nbsp;SPI_IOC_WR_MODE32?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Chaithu&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 04 Dec 2017 11:30:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/iMX6-SPI-Question/m-p/778775#M120981</guid>
      <dc:creator>chaithucheruku</dc:creator>
      <dc:date>2017-12-04T11:30:20Z</dc:date>
    </item>
  </channel>
</rss>

