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    <title>i.MX ProcessorsのトピックRe:  pins state during POR</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/pins-state-during-POR/m-p/777623#M120731</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; There are pin states, provided in the DataSheet(s), relate to situation just after reset ;&lt;/P&gt;&lt;P&gt;pin states during power on \ reset are not guaranteed.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Yuri.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 24 Nov 2017 04:44:17 GMT</pubDate>
    <dc:creator>Yuri</dc:creator>
    <dc:date>2017-11-24T04:44:17Z</dc:date>
    <item>
      <title>pins state during POR</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/pins-state-during-POR/m-p/777621#M120729</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN&gt;Dear Sir&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;I want to ask you about i.MX6ULL.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Q1.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;I want to know the state of the pins during POR is asserted.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Does it have been described in the manual or data sheet?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Best Regards,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Eishi SHIBUSAWA&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 15 Nov 2017 08:37:02 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/pins-state-during-POR/m-p/777621#M120729</guid>
      <dc:creator>eishishibusawa</dc:creator>
      <dc:date>2017-11-15T08:37:02Z</dc:date>
    </item>
    <item>
      <title>Re:  pins state during POR</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/pins-state-during-POR/m-p/777622#M120730</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;refer to the data sheet:&lt;/P&gt;&lt;P&gt;"The SRC_POR_B signal controls the processor POR and must be immediately asserted at&lt;BR /&gt;power-up and remain asserted until the VDD_ARM_CAP, VDD_SOC_CAP, and VDD_PU_CAP&lt;BR /&gt;supplies are stable. VDD_ARM_IN and VDD_SOC_IN may be applied in either order with no&lt;BR /&gt;restrictions."&lt;/P&gt;&lt;P&gt;for more detailed information, pls refer to the Power-Up Sequence of data sheet.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 21 Nov 2017 05:13:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/pins-state-during-POR/m-p/777622#M120730</guid>
      <dc:creator>joanxie</dc:creator>
      <dc:date>2017-11-21T05:13:19Z</dc:date>
    </item>
    <item>
      <title>Re:  pins state during POR</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/pins-state-during-POR/m-p/777623#M120731</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; There are pin states, provided in the DataSheet(s), relate to situation just after reset ;&lt;/P&gt;&lt;P&gt;pin states during power on \ reset are not guaranteed.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Yuri.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 24 Nov 2017 04:44:17 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/pins-state-during-POR/m-p/777623#M120731</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2017-11-24T04:44:17Z</dc:date>
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