i.MX Processorsのトピックi.MX6DQ DC Display Configuration 1 Register

i.MX6DQ DC Display Configuration 1 Register

sugiyamatoshihi — Tue, 09 Jan 2018 10:00:36 GMT

Hi,

I have a question about IPU registers.

There are four registers named DC Display Configuration 1 Register 0 to 3.

I think it configure display #0-3, however each IPU could support only 2 displays.

I know i.MX6DQ has 2 IPUs, and it could support 4 displays, but it seems 8 display could be supported?

Why there is 4 configuration registers?

Best Regards,

Sugiyama

Re: i.MX6DQ DC Display Configuration 1 Register

diegoadrian — Tue, 16 Jan 2018 18:28:18 GMT

Hello

This is because the IPU can support 4 displays. But our chip only has the support for 2 displays for each IPU.

Best Regards,

Diego

Re: i.MX6DQ DC Display Configuration 1 Register

sugiyamatoshihi — Wed, 17 Jan 2018 08:55:18 GMT

Hi, Diago,

I know each IPU support two display, but Dsiplay # is 0 to 4 for each IPU.

I think IPUx_DC_WR_CH_CONF_6, IPUx_DC_WR_CH_CONF_5, IPUx_DC_WR_CH_CONF_2, IPUx_DC_WR_CH_CONF_1 can choose display #0 to #3. Also there are PROG_DI_ID_6, PROG_DI_ID_5, PROG_DI_ID_2, PROG_DI_ID_1 registers that can choose DI0, or DI1.

So, these display combination can select like IPU1 CH5 DI0, display#0, IPU1 CH6 DI1 display #1, IPU1 CH2 display#2, IPU1 CH1 display#4, but it could display only two combination.

Which CH cannot use ? Or if CH Conf set like above which combination is prior to display?

Best Regards,

Sugiyama