i.MX ProcessorsのトピックDDR3L calibration

DDR3L calibration

mrudangshelat — Tue, 09 Jan 2018 06:10:23 GMT

Hi Igor,

Even I am facing the same issue. Not able to calibrate my DDR3L.

We are trying to load uboot usig imx_usb USB loader, but uboot failed to load.

We are able to boot half only and getting upto below consol message.

------

U-Boot 2014.07-08942-g515451c (Jan 02 2018 - 16:53:52)

CPU: Freescale i.MX6D rev1.5 at 792 MHz
Reset cause: POR
Board: Nitrogen6_max
I2C: ready
DRAM: 2 GiB

------

Kindly help us to solve this issue.

Regards,

Mrudang

Re: DDR3L calibration

Yuri — Tue, 09 Jan 2018 08:00:19 GMT

Hello,

Please check PCB design, using Chapter 3 (i.MX6 Layout Recommendations) of the Hardware

Development Guide for i.MX6

https://www.nxp.com/docs/en/user-guide/IMX6DQ6SDLHDG.pdf

In particular, please use to Excel page named “MX6 DRAM Bus Length Check” in “HW Design Checking

List for i.Mx6”, linked below.

https://community.nxp.com/docs/DOC-93819

Have a great day,
Yuri

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Re: DDR3L calibration

mrudangshelat — Tue, 09 Jan 2018 10:37:12 GMT

Hi Yuri,

Thes board was working fine before, but from past couple of days, I am

facing the boot-up fail issue. We are able to flash u-boot image in RAM

using imx_usb loader utility, but dongle is not able to load uboot image

from the RAM.

We are trying to load uboot using imx_usb USB loader, but uboot failed to

load.

I tried to calibrate the DDR but it is failing. We are Micron's using

DDR3L: MT41K512M16HA-125:A. I guess it may have an issue of

identifying Mode Register 1 (MR1) value.

Kindly provide your view.

Thanks & Regards,

Mrudang Shelat

Re: DDR3L calibration

mrudangshelat — Tue, 09 Jan 2018 13:27:43 GMT

Hi,

My faulty board issue is similar with Serial downloader jump error issue.

Thanks & Regards,

Mrudang Shelat

Re: DDR3L calibration

Yuri — Wed, 10 Jan 2018 03:58:19 GMT

Hello,

In addition to checking the design, as mentioned earlier, You may try

to use different drive strength for memory signals.

Have a great day,

Yuri

------------------------------------------------------------------------------

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Re: DDR3L calibration

mrudangshelat — Tue, 16 Jan 2018 13:02:06 GMT

Hi Yuri,

I have tried with changing drive strength but facing the same issue as calibration fail. Please see below reading.

I am using MT41K512M16HA-125:A DDR3L.

-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

============================================
DDR Stress Test (2.6.0)
Build: Aug 1 2017, 17:33:25
NXP Semiconductors.
============================================

============================================
Chip ID
CHIP ID = i.MX6 Dual/Quad (0x63)
Internal Revision = TO1.5
============================================

============================================
Boot Configuration
SRC_SBMR1(0x020d8004) = 0x18000030
SRC_SBMR2(0x020d801c) = 0x02000001
============================================

ARM Clock set to 1GHz

============================================
DDR configuration
BOOT_CFG3[5-4]: 0x00, Single DDR channel.
DDR type is DDR3
Data width: 32, bank num: 8
Row size: 16, col size: 10
Chip select CSD0 is used
Density per chip select: 2048MB
============================================

Current Temperature: 27
============================================

DDR Freq: 396 MHz

ddr_mr1=0x00000000
Start write leveling calibration...
running Write level HW calibration
Write leveling calibration completed, update the following registers in your initialization script
MMDC_MPWLDECTRL0 ch0 (0x021b080c) = 0x00130016
MMDC_MPWLDECTRL1 ch0 (0x021b0810) = 0x00180010
Write DQS delay result:
Write DQS0 delay: 22/256 CK
Write DQS1 delay: 19/256 CK
Write DQS2 delay: 16/256 CK
Write DQS3 delay: 24/256 CK

Starting DQS gating calibration
. HC_DEL=0x00000000 result[00]=0x00001111
. HC_DEL=0x00000001 result[01]=0x00000011
. HC_DEL=0x00000002 result[02]=0x00000000
. HC_DEL=0x00000003 result[03]=0x00000000
. HC_DEL=0x00000004 result[04]=0x00001111
. HC_DEL=0x00000005 result[05]=0x00001111
. HC_DEL=0x00000006 result[06]=0x00001111
. HC_DEL=0x00000007 result[07]=0x00001111
. HC_DEL=0x00000008 result[08]=0x00001111
. HC_DEL=0x00000009 result[09]=0x00001111
. HC_DEL=0x0000000A result[0A]=0x00001111
. HC_DEL=0x0000000B result[0B]=0x00001111
. HC_DEL=0x0000000C result[0C]=0x00001111
. HC_DEL=0x0000000D result[0D]=0x00001111
DQS HC delay value low1 = 0x01010202, high1=0x03030303

loop ABS offset to get HW_DG_LOW
. ABS_OFFSET=0x00000000 result[00]=0x00001111
. ABS_OFFSET=0x00000004 result[01]=0x00001111
. ABS_OFFSET=0x00000008 result[02]=0x00001111
. ABS_OFFSET=0x0000000C result[03]=0x00001100
. ABS_OFFSET=0x00000010 result[04]=0x00001100
. ABS_OFFSET=0x00000014 result[05]=0x00001111
. ABS_OFFSET=0x00000018 result[06]=0x00001111
. ABS_OFFSET=0x0000001C result[07]=0x00001111
. ABS_OFFSET=0x00000020 result[08]=0x00001111
. ABS_OFFSET=0x00000024 result[09]=0x00001111
. ABS_OFFSET=0x00000028 result[0A]=0x00001111
. ABS_OFFSET=0x0000002C result[0B]=0x00001111
. ABS_OFFSET=0x00000030 result[0C]=0x00001111
. ABS_OFFSET=0x00000034 result[0D]=0x00001111
. ABS_OFFSET=0x00000038 result[0E]=0x00001111
. ABS_OFFSET=0x0000003C result[0F]=0x00001100
. ABS_OFFSET=0x00000040 result[10]=0x00001100
. ABS_OFFSET=0x00000044 result[11]=0x00001100
. ABS_OFFSET=0x00000048 result[12]=0x00001100
. ABS_OFFSET=0x0000004C result[13]=0x00001100
. ABS_OFFSET=0x00000050 result[14]=0x00001111
. ABS_OFFSET=0x00000054 result[15]=0x00001100
. ABS_OFFSET=0x00000058 result[16]=0x00001111
. ABS_OFFSET=0x0000005C result[17]=0x00001100
. ABS_OFFSET=0x00000060 result[18]=0x00001100
. ABS_OFFSET=0x00000064 result[19]=0x00001100
. ABS_OFFSET=0x00000068 result[1A]=0x00001100
. ABS_OFFSET=0x0000006C result[1B]=0x00001100
. ABS_OFFSET=0x00000070 result[1C]=0x00001100
. ABS_OFFSET=0x00000074 result[1D]=0x00001100
. ABS_OFFSET=0x00000078 result[1E]=0x00001100
. ABS_OFFSET=0x0000007C result[1F]=0x00001111

loop ABS offset to get HW_DG_HIGH
. ABS_OFFSET=0x00000000 result[00]=0x00000000
. ABS_OFFSET=0x00000004 result[01]=0x00000000
. ABS_OFFSET=0x00000008 result[02]=0x00000000
. ABS_OFFSET=0x0000000C result[03]=0x00000000
. ABS_OFFSET=0x00000010 result[04]=0x00000000
. ABS_OFFSET=0x00000014 result[05]=0x00000000
. ABS_OFFSET=0x00000018 result[06]=0x00000000
. ABS_OFFSET=0x0000001C result[07]=0x00000000
. ABS_OFFSET=0x00000020 result[08]=0x00000000
. ABS_OFFSET=0x00000024 result[09]=0x00000000
. ABS_OFFSET=0x00000028 result[0A]=0x00000000
. ABS_OFFSET=0x0000002C result[0B]=0x00000000
. ABS_OFFSET=0x00000030 result[0C]=0x00000100
. ABS_OFFSET=0x00000034 result[0D]=0x00001100
. ABS_OFFSET=0x00000038 result[0E]=0x00001100
. ABS_OFFSET=0x0000003C result[0F]=0x00001100
. ABS_OFFSET=0x00000040 result[10]=0x00001110
. ABS_OFFSET=0x00000044 result[11]=0x00001110
. ABS_OFFSET=0x00000048 result[12]=0x00001110
. ABS_OFFSET=0x0000004C result[13]=0x00001111
. ABS_OFFSET=0x00000050 result[14]=0x00001111
. ABS_OFFSET=0x00000054 result[15]=0x00001111
. ABS_OFFSET=0x00000058 result[16]=0x00001111
. ABS_OFFSET=0x0000005C result[17]=0x00001111
. ABS_OFFSET=0x00000060 result[18]=0x00001111
. ABS_OFFSET=0x00000064 result[19]=0x00001111
. ABS_OFFSET=0x00000068 result[1A]=0x00001111
. ABS_OFFSET=0x0000006C result[1B]=0x00001111
. ABS_OFFSET=0x00000070 result[1C]=0x00001111
. ABS_OFFSET=0x00000074 result[1D]=0x00001111
. ABS_OFFSET=0x00000078 result[1E]=0x00001111
. ABS_OFFSET=0x0000007C result[1F]=0x00001111

BYTE 0:
Start: HC=0x01 ABS=0x5C
End: HC=0x03 ABS=0x48
Mean: HC=0x02 ABS=0x52
End-0.5*tCK: HC=0x02 ABS=0x48
Final: HC=0x02 ABS=0x52
BYTE 1:
Start: HC=0x01 ABS=0x5C
End: HC=0x03 ABS=0x3C
Mean: HC=0x02 ABS=0x4C
End-0.5*tCK: HC=0x02 ABS=0x3C
Final: HC=0x02 ABS=0x4C
BYTE 2:
Start: HC=0x01 ABS=0x00
End: HC=0x03 ABS=0x2C
Mean: HC=0x02 ABS=0x16
End-0.5*tCK: HC=0x02 ABS=0x2C
Final: HC=0x02 ABS=0x2C
BYTE 3:
Start: HC=0x01 ABS=0x00
End: HC=0x03 ABS=0x30
Mean: HC=0x02 ABS=0x18
End-0.5*tCK: HC=0x02 ABS=0x30
Final: HC=0x02 ABS=0x30

DQS calibration MMDC0 MPDGCTRL0 = 0x024C0252, MPDGCTRL1 = 0x0230022C

Note: Array result[] holds the DRAM test result of each byte.
0: test pass. 1: test fail
4 bits respresent the result of 1 byte.
result 0001:byte 0 fail.
result 0011:byte 0, 1 fail.

Starting Read calibration...

ABS_OFFSET=0x00000000 result[00]=0x1111
ABS_OFFSET=0x04040404 result[01]=0x1111
ABS_OFFSET=0x08080808 result[02]=0x1011
ABS_OFFSET=0x0C0C0C0C result[03]=0x1011
ABS_OFFSET=0x10101010 result[04]=0x1011
ABS_OFFSET=0x14141414 result[05]=0x0011
ABS_OFFSET=0x18181818 result[06]=0x0011
ABS_OFFSET=0x1C1C1C1C result[07]=0x0000
ABS_OFFSET=0x20202020 result[08]=0x0000
ABS_OFFSET=0x24242424 result[09]=0x0000
ABS_OFFSET=0x28282828 result[0A]=0x0000
ABS_OFFSET=0x2C2C2C2C result[0B]=0x0000
ABS_OFFSET=0x30303030 result[0C]=0x0000
ABS_OFFSET=0x34343434 result[0D]=0x0000
ABS_OFFSET=0x38383838 result[0E]=0x0000
ABS_OFFSET=0x3C3C3C3C result[0F]=0x0000
ABS_OFFSET=0x40404040 result[10]=0x0000
ABS_OFFSET=0x44444444 result[11]=0x0000
ABS_OFFSET=0x48484848 result[12]=0x0000
ABS_OFFSET=0x4C4C4C4C result[13]=0x0000
ABS_OFFSET=0x50505050 result[14]=0x0000
ABS_OFFSET=0x54545454 result[15]=0x0000
ABS_OFFSET=0x58585858 result[16]=0x0000
ABS_OFFSET=0x5C5C5C5C result[17]=0x0000
ABS_OFFSET=0x60606060 result[18]=0x0000
ABS_OFFSET=0x64646464 result[19]=0x0010
ABS_OFFSET=0x68686868 result[1A]=0x0110
ABS_OFFSET=0x6C6C6C6C result[1B]=0x1111
ABS_OFFSET=0x70707070 result[1C]=0x1111
ABS_OFFSET=0x74747474 result[1D]=0x1111
ABS_OFFSET=0x78787878 result[1E]=0x1111
ABS_OFFSET=0x7C7C7C7C result[1F]=0x1111

Byte 0: (0x1c - 0x68), middle value:0x42
Byte 1: (0x1c - 0x60), middle value:0x3e
Byte 2: (0x08 - 0x64), middle value:0x36
Byte 3: (0x14 - 0x68), middle value:0x3e

MMDC0 MPRDDLCTL = 0x3E363E42

Starting Write calibration...

ABS_OFFSET=0x00000000 result[00]=0x1111
ABS_OFFSET=0x04040404 result[01]=0x1111
ABS_OFFSET=0x08080808 result[02]=0x0011
ABS_OFFSET=0x0C0C0C0C result[03]=0x0001
ABS_OFFSET=0x10101010 result[04]=0x0011
ABS_OFFSET=0x14141414 result[05]=0x0011
ABS_OFFSET=0x18181818 result[06]=0x0011
ABS_OFFSET=0x1C1C1C1C result[07]=0x0011
ABS_OFFSET=0x20202020 result[08]=0x0011
ABS_OFFSET=0x24242424 result[09]=0x0011
ABS_OFFSET=0x28282828 result[0A]=0x0011
ABS_OFFSET=0x2C2C2C2C result[0B]=0x0011
ABS_OFFSET=0x30303030 result[0C]=0x0011
ABS_OFFSET=0x34343434 result[0D]=0x0001
ABS_OFFSET=0x38383838 result[0E]=0x0001
ABS_OFFSET=0x3C3C3C3C result[0F]=0x0001
ABS_OFFSET=0x40404040 result[10]=0x0001
ABS_OFFSET=0x44444444 result[11]=0x0001
ABS_OFFSET=0x48484848 result[12]=0x0001
ABS_OFFSET=0x4C4C4C4C result[13]=0x0001
ABS_OFFSET=0x50505050 result[14]=0x0001
ABS_OFFSET=0x54545454 result[15]=0x0001
ABS_OFFSET=0x58585858 result[16]=0x0001
ABS_OFFSET=0x5C5C5C5C result[17]=0x0001
ABS_OFFSET=0x60606060 result[18]=0x0001
ABS_OFFSET=0x64646464 result[19]=0x0001
ABS_OFFSET=0x68686868 result[1A]=0x0001
ABS_OFFSET=0x6C6C6C6C result[1B]=0x0001
ABS_OFFSET=0x70707070 result[1C]=0x0001
ABS_OFFSET=0x74747474 result[1D]=0x1111
ABS_OFFSET=0x78787878 result[1E]=0x1111
ABS_OFFSET=0x7C7C7C7C result[1F]=0x1111

ERROR FOUND, we can't get suitable value !!!!
dram test fails for all values.

Error: failed during ddr calibration

-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

Please go through attached files and provide me your valuable feedback.

Thanks,

Mrudang