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    <title>i.MX ProcessorsのトピックRe: Based on i.mx7ulp porting LPDDR2 SDRAM</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Based-on-i-mx7ulp-porting-LPDDR2-SDRAM/m-p/771427#M119779</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="color: #e9e3d5; background-color: #212127;"&gt;Dear&lt;/SPAN&gt;&lt;SPAN style="background-color: #212127; color: #cbbeaa; font-size: 18.004px;"&gt;&amp;nbsp;igorpadykov&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #e9e3d5; background-color: #212127;"&gt;Thanks for your help, you do gave me a big favor.&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 13 Jun 2018 02:10:00 GMT</pubDate>
    <dc:creator>sam_liu</dc:creator>
    <dc:date>2018-06-13T02:10:00Z</dc:date>
    <item>
      <title>Based on i.mx7ulp porting LPDDR2 SDRAM</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Based-on-i-mx7ulp-porting-LPDDR2-SDRAM/m-p/771425#M119777</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello everyone,&lt;/P&gt;&lt;P&gt;&amp;nbsp; I'm new here,could you give me a few pointers with LPDDR2 SDRAM porting.&lt;/P&gt;&lt;P&gt;&amp;nbsp; In my project, it's base on i.mx7ulp and the original Yocto BSP is set for LPDDR3.&lt;BR /&gt;Now I want to change the LPDDR3 to LPDDR2(1G) for my project's design, I already use the LPDDR2_RegisterProgrammingAid_V0_2.xlsx to create LPDDR2 relate setting register parameter in RealView.inc file.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;According to "I.MX BSP Porting Guide " I already do some edit but I still have some question as below :&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;1. Whether I only need according to the register setting sequence and value in RealView.inc fill all parameter into the "imximage.cfg file" and then rebuild : bitbake -f -c compile u-boot-imx ?&lt;/P&gt;&lt;P&gt;Is there any files need to modify for porting SDRAM form LPDDR3 change to LPDDR2 ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;2. If the register setting sequence in imximage.cfg file is not match RealView.inc file , it will lead to an error or not?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;3. Does the mx7ulp_evk.h file need to modify?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;4.The //PCC0 ,//PCC1 and //PCC2 relate register setting in "RealView.inc file" are all set to value: 0x40000000 , whether I don't need fill these setting into imximage.cfg file?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;5. The plugin.S file in git/board/freescale/mx7ulp_evk need to modify or not ? Does this file will be used when u-boot in boot phase?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thank~&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 11 Jun 2018 10:18:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Based-on-i-mx7ulp-porting-LPDDR2-SDRAM/m-p/771425#M119777</guid>
      <dc:creator>sam_liu</dc:creator>
      <dc:date>2018-06-11T10:18:26Z</dc:date>
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      <title>Re: Based on i.mx7ulp porting LPDDR2 SDRAM</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Based-on-i-mx7ulp-porting-LPDDR2-SDRAM/m-p/771426#M119778</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Sam&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;example of lpddr2 configuration can be found in&lt;/P&gt;&lt;P&gt;linux/board/freescale/mx7ulp_arm2&amp;nbsp; imximage_lpddr2.cfg &lt;BR /&gt;&lt;A class="jive-link-external-small" href="https://community.nxp.com/external-link.jspa?url=https%3A%2F%2Fsource.codeaurora.org%2Fexternal%2Fimx%2Fuboot-imx%2Ftree%2Fboard%2Ffreescale%2Fmx7ulp_arm2%3Fh%3Dimx_v2017.03_4.9.88_2.0.0_ga" rel="nofollow" target="_blank"&gt;https://source.codeaurora.org/external/imx/uboot-imx/tree/board/freescale/mx7ulp_arm2?h=imx_v2017.03_4.9.88_2.0.0_ga&lt;/A&gt;&lt;BR /&gt;plugin.S file is not needed if plugin mode is not used (more description can be found in Boot&lt;/P&gt;&lt;P&gt;Chapter of Reference Manual). &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;gt;Does the mx7ulp_evk.h file need to modify?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;no&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;gt;Is there any files need to modify for porting SDRAM form LPDDR3 change to LPDDR2 ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;except *.cfg file, in&amp;nbsp; linux/arch/arm/mach-imx&amp;nbsp; there are specific for memory low power codes&lt;BR /&gt;&lt;A href="https://source.codeaurora.org/external/imx/linux-imx/tree/arch/arm/mach-imx?h=imx_4.9.88_2.0.0_ga"&gt;https://source.codeaurora.org/external/imx/linux-imx/tree/arch/arm/mach-imx?h=imx_4.9.88_2.0.0_ga&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 12 Jun 2018 05:17:33 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Based-on-i-mx7ulp-porting-LPDDR2-SDRAM/m-p/771426#M119778</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2018-06-12T05:17:33Z</dc:date>
    </item>
    <item>
      <title>Re: Based on i.mx7ulp porting LPDDR2 SDRAM</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Based-on-i-mx7ulp-porting-LPDDR2-SDRAM/m-p/771427#M119779</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;&lt;SPAN style="color: #e9e3d5; background-color: #212127;"&gt;Dear&lt;/SPAN&gt;&lt;SPAN style="background-color: #212127; color: #cbbeaa; font-size: 18.004px;"&gt;&amp;nbsp;igorpadykov&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN style="color: #e9e3d5; background-color: #212127;"&gt;Thanks for your help, you do gave me a big favor.&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 13 Jun 2018 02:10:00 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Based-on-i-mx7ulp-porting-LPDDR2-SDRAM/m-p/771427#M119779</guid>
      <dc:creator>sam_liu</dc:creator>
      <dc:date>2018-06-13T02:10:00Z</dc:date>
    </item>
    <item>
      <title>Re: Based on i.mx7ulp porting LPDDR2 SDRAM</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Based-on-i-mx7ulp-porting-LPDDR2-SDRAM/m-p/771428#M119780</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear igorpadykov&lt;/P&gt;&lt;P&gt;&amp;nbsp; Can I ask you to do me a favour?&amp;nbsp;I already fill in&amp;nbsp; LPDDR2 parameters into "imximage.cfg" refer to&amp;nbsp;&amp;nbsp;"linux/board/freescale/mx7ulp_arm2&amp;nbsp; imximage_lpddr2.cfg" as you mentioned previously, but now I face another problem is the u-boot stuck and it doesn't show any message&amp;nbsp;at UART port on my_customer board&amp;nbsp;&lt;SPAN&gt;during&lt;/SPAN&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;boot stage.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; Because my_customer board is boot from uSD-Card, so I measured both&amp;nbsp; "CLK" and "DATA0" signals&amp;nbsp; on uSD-card to confirm&amp;nbsp;u-boot process is fail.&lt;/P&gt;&lt;P&gt;&amp;nbsp; I find that "CLK" and "DATA0" signals will continue normal active on NXP-EVB&amp;nbsp;during&amp;nbsp;boot stage (fig 1.) ,but&amp;nbsp; both these two signal on my_ customer board only active&amp;nbsp;at the beginning during boot stage and then will STOP&amp;nbsp;&lt;SPAN&gt;(fig 2.)&amp;nbsp;&lt;/SPAN&gt;.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="nxp_evb.jpg"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/62477i190106663E0A7573/image-size/large?v=v2&amp;amp;px=999" role="button" title="nxp_evb.jpg" alt="nxp_evb.jpg" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; &amp;nbsp; fig 1 . Red : DATA0&amp;nbsp; Green: CKL on&amp;nbsp; NXP -EVB during boot stage.&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="my_board.jpg"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/62478iC56AF3E89B4508FB/image-size/large?v=v2&amp;amp;px=999" role="button" title="my_board.jpg" alt="my_board.jpg" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&lt;SPAN&gt;&amp;nbsp;fig 2 . Red : D&lt;/SPAN&gt;&lt;SPAN&gt;ATA0&amp;nbsp; Green: CKL on&amp;nbsp;&amp;nbsp;MY- Board&amp;nbsp;during boot stage.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;these are&amp;nbsp; what I&amp;nbsp;modified in BSP as below :&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;1. change setting in&amp;nbsp;&amp;nbsp;"mx7ulp_evk.c" uart port to match my_customer board design.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;2.&amp;nbsp;imx7ulp.dtsi(in U-boot) (for match my_customer&amp;nbsp;&lt;SPAN&gt;design&lt;/SPAN&gt;)&lt;/P&gt;&lt;P&gt;&amp;nbsp;3.&amp;nbsp;imx7ulp-evk.dts&lt;SPAN&gt;(in U-boot)&amp;nbsp;(for match my_customer&amp;nbsp;&lt;SPAN&gt;design&lt;/SPAN&gt;&lt;SPAN&gt;)&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;4. imximage.cfg.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;5. And I re-build "bitbake u-boot-imx" with no error.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;My question is shown as below :&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;1. Actually ,relate to porting DDR process in the "i.MX BSP Porting Guide" only mention in chapter&amp;nbsp; "3.2.1 Changing the DCD table for i.MX DDR initialization "&amp;nbsp; , it's just indicate that we need to modify my_board.cfg.&lt;/P&gt;&lt;P&gt;I really want to known is HOW should I do to fill in DCD table parameters&amp;nbsp; refer to RealView.inc ?&lt;/P&gt;&lt;P&gt;Is these any document can show&amp;nbsp; more detail about modify the DCD table?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;2. Whether the modified of device tree&amp;nbsp; in u-boot source file will cause a u-boot fail?&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp; ( The modified "u-boot-imx" image&amp;nbsp; doesn't show any error message when I re-build it . )&amp;nbsp;&lt;/P&gt;&lt;P&gt;&amp;nbsp;3. According to fig 2. wave form ,could you give me some tips about this case ? Is the DCD table configuration mistake cause this case ?or device tree configuration mistake in u-boot source code?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 27 Jun 2018 06:42:28 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Based-on-i-mx7ulp-porting-LPDDR2-SDRAM/m-p/771428#M119780</guid>
      <dc:creator>sam_liu</dc:creator>
      <dc:date>2018-06-27T06:42:28Z</dc:date>
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