topic Re: HDMI influence on MIPI in i.MX Processors

HDMI influence on MIPI

pierre-olivierh — Fri, 23 Feb 2018 15:13:26 GMT

Hello,

We found a really strange issue with a MIPI camera and HDMI.

Our MIPI camera works fine, is correctly configured and works with Gstreamer. But if we activate the HDMI ( by inserting the correct vidargs in u-boot : vidargs=video=mxcfb0:dev=hdmi,1920x1080M@60,if=RGB24;video=mxcfb1:off fbmem=32M) the video "make a roll" when we restart Gstreamer.

This issue only happens when the HDMI is enabled in u-boot.

Another strange issue: when we disabled mxcfb* in the device tree:

&mxcfb1 { 
status = "disabled";
};
&mxcfb2 { 
status = "disabled";
};
&mxcfb3 { 
status = "disabled";
};
&mxcfb4 { 
status = "disabled";
};‍‍‍‍‍‍‍‍‍‍‍‍

The MIPI does not work at all, the MIPI_CSI_PHY_STATE is constantly equals to 0x200

Any thoughts about this issue? Is it clock related?

We are working on iMX6Q POP package, the MIPI is running at 648MHz.

The image is build by Yocto Pyro, kernel is 4.1.15.

Regards,

Pierre-Olivier

Re: HDMI influence on MIPI

igorpadykov — Fri, 23 Feb 2018 23:46:39 GMT

Hi Pierre-Olivier

what bsp and gstreamer used in the case. One can try with nxp official

demo images from

Board Support Packages (3)
Demo Images - QWKS Board based on SCM-i.MX 6D/Q

Quick Start Board for SCM-i.MX 6DQ|NXP

Yocto BSP for SCM-i.MX L4.1.15-2.0.0_ga

Best regards
igor
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Re: HDMI influence on MIPI

pierre-olivierh — Thu, 19 Jul 2018 10:20:22 GMT

Hi Igor,

Thank you for the answer.

It is quite complicated to test the official Yocto BSP, we have to port all our modifications.

We use the Variscite BSP (with some little customisations), with Yocto Pyro, with Gstreamer 1.10.4.

But I have something interesting, the clocks are not the same with or without the HDMI enabled in uboot:

When I disable hdmi via uboot:

pll5 is at 1.188GHz, and is reduced to 296.6MHz
ipu1_pclk0 clock source become ipu1_sel (instead of ipu1_di0)
ipu1_pclk enable_count (1 with HDMI) becomes 0

This is the two gists with the complete clock summary

My question:

As I understand the iMX6, the IPUx DI are used for display ports/VGA, so why the ipu1_di clock is used (enable_cnt=1) if I only use HDMI?

Regards,

Re: HDMI influence on MIPI

pierre-olivierh — Fri, 20 Jul 2018 13:23:20 GMT

Update:

After my response on the clocks (with or without HDMI), I did some other tests.

My configuration is as follow:

IPU1_CSI0 and IPU1_CSI1 are used by a MIPI source (on virtual channel 0 and 1)

IPU2_CSI1 is used by a parallel camera in BT656.

IPU2_CSI0 is unused

Everything is working, excepted the video scroll.

I get these messages when the video is scrolling, the scroll stops when the video bottom hit the bottom of the screen.

[ 4118.492325] imx-ipuv3 2400000.ipu: IPU Warning - IPU_INT_STAT_5 = 0x00000001

The message is sent multiple times during the scroll

At the begining of my test, my configuration is:

IPUx hsp clock set to 198MHz
IPU1_di0 (because hdmi_core in dtb is on ipu0 di0) is set to 145.8MHz (1080p60)

What I tried:

I tried to increase HSP clock of both IPUs to 270MHz, still scrolling.
I tried to change the hdmi_core ipux_dix to IPU2_DI0 (in dtb): the MIPI on IPU1 worked well, no video scroll, BUT the parallel video on IPU1 was scrolling...
So I tried to set all IPU clocks to 148.5: the HSP and the IPUx_DIx. The HDMI on the IPU1 is still scrolling and the parallel video did not work well (148.5MHz is the BT656 video clock).
Last attempt: IPU1_hsp is set to 148.5, IPU2_hsp is set to 270MHz. the hdmi core is set on IPU1_di0. The MIPI is still scrolling (as expected) but the message (IPU_INT_STAT_5=0x01) appear only one time

Any thoughts? Any advices on something I am doing wrong?