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    <title>i.MX ProcessorsのトピックRe: IMX6 SPI Native Chip Select</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/IMX6-SPI-Native-Chip-Select/m-p/770293#M119599</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Parag&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;for hardware trigger (HT) mode please look at&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/thread/469174"&gt;HT mode is not supported by imx6ul&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;It is not related with native chip select assertion timing.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 31 Jan 2018 11:03:50 GMT</pubDate>
    <dc:creator>igorpadykov</dc:creator>
    <dc:date>2018-01-31T11:03:50Z</dc:date>
    <item>
      <title>IMX6 SPI Native Chip Select</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6-SPI-Native-Chip-Select/m-p/770292#M119598</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello ,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We are trying to enable Native Chip Select for IMX6 UL Processor.&lt;/P&gt;&lt;P&gt;We are able to communicate with Slave device by configuring the IMX6 as master using GPIO Chip select.&lt;/P&gt;&lt;P&gt;But when we change the DTS configuration and Period register accordingly we do not see any response from Slave device.&lt;/P&gt;&lt;P&gt;I have a query: What is the function of "Hardware Trigger and Hardware Trigger Length " in IMX6UL ?&lt;/P&gt;&lt;P&gt;Is it related with Native chip select assertion timing ?&lt;/P&gt;&lt;P&gt;As there is very little description, i would request if someone can put some useful information and let me know if any issues operating IMX6UL SPI in native chip select mode.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 31 Jan 2018 08:43:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6-SPI-Native-Chip-Select/m-p/770292#M119598</guid>
      <dc:creator>hrishikesh23</dc:creator>
      <dc:date>2018-01-31T08:43:24Z</dc:date>
    </item>
    <item>
      <title>Re: IMX6 SPI Native Chip Select</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX6-SPI-Native-Chip-Select/m-p/770293#M119599</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Parag&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;for hardware trigger (HT) mode please look at&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/thread/469174"&gt;HT mode is not supported by imx6ul&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;It is not related with native chip select assertion timing.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 31 Jan 2018 11:03:50 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX6-SPI-Native-Chip-Select/m-p/770293#M119599</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2018-01-31T11:03:50Z</dc:date>
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