Customized QuadSPI Look-up Table/Flash Access Scheme

martinzohlhuber — Mon, 08 Jan 2018 15:51:18 GMT

Hello

i.MX 7Dual Applications Processor Reference Manual, Rev. 0.1, 08/2016

implies (Section Flash Devices) that a user can create customized QuadSPI Instruction with Look-up Table and Programmable Sequence Engine.

Figure 10-17. Serial Flash Access Scheme illustrates a pattern:

Instruction (1 Byte) – Address (3/4 Byte) – Mode (1 Byte) – Dummy (max 64 Byte) – Data

My Quad-SPI Device expects scheme:

Instruction (1 Byte) – Address (4 Byte) – Value (2+ Byte) – Dummy (max 16) – Data

With “Value” are two byte sent from i.MX to the device (like length of the data to be read/written)

Is it possible to define such a scheme?

How should the Look-Up Table be defined?

CMD | 0xAB

ADDR | 0x20

???? | 0x0004

DUMMY | 0x0A

READ | 0x04

STOP | 0x00

Thanks

Martin

Re: Customized QuadSPI Look-up Table/Flash Access Scheme

igorpadykov — Tue, 09 Jan 2018 08:21:07 GMT

Hi Martin

yes such sequence can be defined, please look at examples in

sect.10.2.8.1 Example Sequences i.MX7D Reference Manual

http://cache.nxp.com/files/32bit/doc/ref_manual/IMX7DRM.pdf

Best regards
igor
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i.MX ProcessorsのトピックRe: Customized QuadSPI Look-up Table/Flash Access Scheme

Customized QuadSPI Look-up Table/Flash Access Scheme

Re: Customized QuadSPI Look-up Table/Flash Access Scheme