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    <title>topic Re: LVDS disabling DE sync signal in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/LVDS-disabling-DE-sync-signal/m-p/769330#M119476</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Igor&lt;/P&gt;&lt;P&gt;Thanks for your reaction. In the meantime we found that our problems are likely caused by hardware.&lt;/P&gt;&lt;P&gt;The LCD is connected to a Solidrun SOM by short matched differential pair traces ( 61mm long) . 4 layer PCB with good groundlayer. We cannot imaginge what is going wrong.&lt;/P&gt;&lt;P&gt;The LCD works OK when connected to a VGA-LVDS board. We copied the timingparameters from this board.&amp;nbsp;Still troubles with some boards/LCD's. Mostly not reproducable.&lt;/P&gt;&lt;P&gt;The VGA-LVDS board also produces all sync signals.&amp;nbsp; If we connect a LVDS to TTL converter board to our PCB we can measure the sync clk etc. All is Ok, so it is not caused by the imx.&lt;/P&gt;&lt;P&gt;Ideas welcome!&lt;/P&gt;&lt;P&gt;Dig&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 23 Nov 2017 14:17:37 GMT</pubDate>
    <dc:creator>digkleppe</dc:creator>
    <dc:date>2017-11-23T14:17:37Z</dc:date>
    <item>
      <title>LVDS disabling DE sync signal</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/LVDS-disabling-DE-sync-signal/m-p/769328#M119474</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;Case: LVDS display on imx6 Solo Linux 3.14&lt;/P&gt;&lt;P&gt;The display sometimes gets out of sync. The LCD can work wit H-and Vsync or DE. The LCD datasheet says nothing about supplying all syncs.&lt;/P&gt;&lt;P&gt;We measured that all these signals are present in the LVDS data. We expected&amp;nbsp; that when the hsync-active,&amp;nbsp; vsync-active and de-active when not mentioned in the DTB these would be ignored. The corresponding&amp;nbsp; LVDS bits should be low (or high?).&lt;/P&gt;&lt;P&gt;We measured that all the signals are present. It seems that this is the reason for our troubles.&lt;/P&gt;&lt;P&gt;I found this post: &amp;nbsp; &amp;nbsp; &lt;A _jive_internal="true" href="https://community.nxp.com/thread/302384"&gt;https://community.nxp.com/thread/302384 &lt;/A&gt;&lt;/P&gt;&lt;P&gt;The H-and V sync cannot be disabled. How about the DE?&lt;/P&gt;&lt;P&gt;Dig&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 13 Nov 2017 13:12:07 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/LVDS-disabling-DE-sync-signal/m-p/769328#M119474</guid>
      <dc:creator>digkleppe</dc:creator>
      <dc:date>2017-11-13T13:12:07Z</dc:date>
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    <item>
      <title>Re: LVDS disabling DE sync signal</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/LVDS-disabling-DE-sync-signal/m-p/769329#M119475</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Dig&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;gt;The H-and V sync cannot be disabled. How about the DE?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;it is the same, as all these signals are defined in ipu microcode (ipu_disp.c) producing&lt;/P&gt;&lt;P&gt;timings according to sect.4.11.10.6.1 IPU Display Operating Signals i.MX6DQ Datasheet&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="http://www.nxp.com/docs/en/data-sheet/IMX6DQCEC.pdf" title="http://www.nxp.com/docs/en/data-sheet/IMX6DQCEC.pdf"&gt;http://www.nxp.com/docs/en/data-sheet/IMX6DQCEC.pdf&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;please check similar thread&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/thread/279078"&gt;How to change IMX53 VGA HSYNC from DI1_PIN7 to DI1_PIN4 -blog archive&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 21 Nov 2017 10:37:15 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/LVDS-disabling-DE-sync-signal/m-p/769329#M119475</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2017-11-21T10:37:15Z</dc:date>
    </item>
    <item>
      <title>Re: LVDS disabling DE sync signal</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/LVDS-disabling-DE-sync-signal/m-p/769330#M119476</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Igor&lt;/P&gt;&lt;P&gt;Thanks for your reaction. In the meantime we found that our problems are likely caused by hardware.&lt;/P&gt;&lt;P&gt;The LCD is connected to a Solidrun SOM by short matched differential pair traces ( 61mm long) . 4 layer PCB with good groundlayer. We cannot imaginge what is going wrong.&lt;/P&gt;&lt;P&gt;The LCD works OK when connected to a VGA-LVDS board. We copied the timingparameters from this board.&amp;nbsp;Still troubles with some boards/LCD's. Mostly not reproducable.&lt;/P&gt;&lt;P&gt;The VGA-LVDS board also produces all sync signals.&amp;nbsp; If we connect a LVDS to TTL converter board to our PCB we can measure the sync clk etc. All is Ok, so it is not caused by the imx.&lt;/P&gt;&lt;P&gt;Ideas welcome!&lt;/P&gt;&lt;P&gt;Dig&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 23 Nov 2017 14:17:37 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/LVDS-disabling-DE-sync-signal/m-p/769330#M119476</guid>
      <dc:creator>digkleppe</dc:creator>
      <dc:date>2017-11-23T14:17:37Z</dc:date>
    </item>
    <item>
      <title>Re: LVDS disabling DE sync signal</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/LVDS-disabling-DE-sync-signal/m-p/769331#M119477</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Update:&lt;/P&gt;&lt;P&gt;We noticed that the LCD was getting initialized 2 times: in the kernel and when the user (QT) program was started.&amp;nbsp; Both are needed. When the second init took place the LVDS signals dropped for a short time. In a trial-and-error way I have put a LVDS buffer between LCD and imx. Then no more problems.&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 17 Sep 2018 06:16:07 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/LVDS-disabling-DE-sync-signal/m-p/769331#M119477</guid>
      <dc:creator>digkleppe</dc:creator>
      <dc:date>2018-09-17T06:16:07Z</dc:date>
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