topic Re: Bare metal ethernet implementation for the cortex M4 in i.MX Processors

Bare metal ethernet implementation for the cortex M4

belicstefan — Sun, 10 Jun 2018 14:45:35 GMT

Hallo everyone, i am trying to implement a bare metal applikation for the cortex M4 that send ethernet frames at defined intervals. I have read the datasheet on how the ethernet registers are setup and the options it offers, but i was not able to understand how the data is actually moved to and from the ethernet FIFO. In the block diagram its shown that an uDMA is used, but no explanation on how to access it are given. It would be great if someone has more information, or even an simple answer on how to do it.

Re: Bare metal ethernet implementation for the cortex M4

Carlos_Musich — Mon, 11 Jun 2018 21:35:39 GMT

Hi,

Unfortunately we dont have baremetal Ethernet examples as it is not common to use this module without a TCP/IP stack.

Is it completely necessary to be baremetal? If you share details on your application we can try to find an alternative for you.

I have a presentation which explains alittle bit more about how the buffers work, but you may need to enter a case at www.nxp.com/support

Regards,
Carlos
NXP Technical Support
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Re: Bare metal ethernet implementation for the cortex M4

belicstefan — Mon, 11 Jun 2018 22:02:49 GMT

Thanks for your replay, it's sad to hear that there are no examples for it. And sadly yes the application has to be bear metal. It has to implement TTEthernet and for that it needs to create specific raw frames.

Either way thanks for your time.