i.MX ProcessorsのトピックRe: iMX6 MMDC refresh schemes

iMX6 MMDC refresh schemes

PiVo — Fri, 16 Mar 2018 19:37:36 GMT

Hi,

Could you confirm that the table 44-8 (MMDC refreshscheme) in IMX6DQRM.pdf) is actually correct? The text mentions that all configurations meet 3.9us refresh time... But to me it seems that 1 = 1,9us and 2 = 7,8us; An error in the document?

Additionally, could you elaborate on how option 1..4 "configure the desired AXI accesses delay/latency in each refresh cycle"? Why not always used the 4th?

Thanks in advance,

Pieter

Re: iMX6 MMDC refresh schemes

Yuri — Mon, 19 Mar 2018 06:26:02 GMT

Hello,

Looks like You are right. For more details look at at section 44.12.9 [MMDC Core Refresh Control

Generally it is recommended to consider only bit field REFR as programmable ;

all other parameters usually are fixed as follows:

REF_CNT: 0x0 (default value, parameter not used)

REF_SEL: 0x1 (choose 32KHz clock to trigger refresh cycle)

START_REF: Manually start refresh cycle, set to 0 for normal operations.

When considering high temperature refresh configuration for the Micron part, it is enough to change

only REF_SEL bit field (0, 64 KHz), assuming other bits are the same as for normal temperature case.

Have a great day,
Yuri

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Re: iMX6 MMDC refresh schemes

PiVo — Mon, 19 Mar 2018 10:51:12 GMT

Hi Yuri,

Thanks for your swift reply! We are looking into memory issues that are related to the rowhammer test patterns. Even with correctly configured memory, this test can flip bits in adjacent rows...

Regarding the 32kHz clock -> does this have the same clock-source as the watchdog??

On our design we does not have a 32khz crystal connected (and uses the internal generated one). I know from experience that this clock is very inaccurate. When using this clock for memory refresh timing (for 7,8us), refreshes will be outside of the JEDEC spec.

Doubling it to 3,9us will make it conform to spec but it will be at the cost of ~1% performance loss...

Best regards, Pieter

Re: iMX6 MMDC refresh schemes

Yuri — Mon, 26 Mar 2018 03:44:09 GMT

Hello,

I do not think, that 32 KHz clock accuracy affects memory refreshing under normal

temperature condition. In any case it is possible to try double (64 KHz) frequency

configuration.

Regards,

Yuri.

Re: iMX6 MMDC refresh schemes

TomE — Thu, 18 Oct 2018 23:23:58 GMT

Where does the 64kHz come from? Is it a frequency-doubled 32kHz?

This customer found that if you don't GROUND the RTC_XTAL1 pin the internal oscillator doesn't work, and so the memory isn't refreshed, or is only intermittently refreshed. Could this have been your problem?

https://community.nxp.com/message/1069787

Tom