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    <title>i.MX Processors中的主题 Re: Question, i.MX8M schematic design</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX8M-schematic-design/m-p/767364#M119174</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi &lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/Yuri"&gt;Yuri&lt;/A&gt;‌&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Noted with thanks !&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;BR,&lt;/P&gt;&lt;P&gt;Miyamoto&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 27 Apr 2018 03:26:16 GMT</pubDate>
    <dc:creator>SLICE</dc:creator>
    <dc:date>2018-04-27T03:26:16Z</dc:date>
    <item>
      <title>Question, i.MX8M schematic design</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX8M-schematic-design/m-p/767358#M119168</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear team,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;(1)&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;I would like to ask about HDMI_REFCLK_P/N ports of i.MX8M.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Could you show me whether these pins are used only for HDMI circuitry inside of i.MX?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;If these pins are used for other circuitry, please let me know.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;My customer saw that your Hardware Developer’s Guide says that those pins can be left open when unused, but they want to know those pins are really used ONLY for HDMI.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;(2)&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Could you show me the way to treat PCIe_RXN_P/N pins of i.MX8M if PCIe is unused?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Thanks,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Miyamoto&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 25 Apr 2018 05:14:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX8M-schematic-design/m-p/767358#M119168</guid>
      <dc:creator>SLICE</dc:creator>
      <dc:date>2018-04-25T05:14:24Z</dc:date>
    </item>
    <item>
      <title>Re: Question, i.MX8M schematic design</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX8M-schematic-design/m-p/767359#M119169</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;1.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; The fact, that HDMI_REFCLK clock may be left floating, when HDMI is not used,&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;without any additional comments in the Hardware Guide, means, that only HDMI&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;module is affected by this clock.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;2.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; According to Table 30 (i.MX8M Unused Signal Strapping Recommendations) &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;of the Hardware Guide, PCIe_RXN_P/N are commented to leave unconnected.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="https://www.nxp.com/docs/en/user-guide/IMX8MDQLQHDG.pdf" title="https://www.nxp.com/docs/en/user-guide/IMX8MDQLQHDG.pdf"&gt;https://www.nxp.com/docs/en/user-guide/IMX8MDQLQHDG.pdf&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 25 Apr 2018 05:56:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX8M-schematic-design/m-p/767359#M119169</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2018-04-25T05:56:59Z</dc:date>
    </item>
    <item>
      <title>Re: Question, i.MX8M schematic design</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX8M-schematic-design/m-p/767360#M119170</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi &lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/Yuri"&gt;Yuri&lt;/A&gt;‌&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks for your prompt reply.&lt;/P&gt;&lt;P&gt;2.&lt;/P&gt;&lt;P&gt;Actually, we could not find the description about PCIE_RXNxx in your Developer's Guide.&lt;/P&gt;&lt;P&gt;Is it really OK for these pins to leave open?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Miyamoto&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 25 Apr 2018 06:19:29 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX8M-schematic-design/m-p/767360#M119170</guid>
      <dc:creator>SLICE</dc:creator>
      <dc:date>2018-04-25T06:19:29Z</dc:date>
    </item>
    <item>
      <title>Re: Question, i.MX8M schematic design</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX8M-schematic-design/m-p/767361#M119171</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Yes.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="PCIe_8.jpg"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/57638i354187882B6C271F/image-size/large?v=v2&amp;amp;px=999" role="button" title="PCIe_8.jpg" alt="PCIe_8.jpg" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 25 Apr 2018 06:42:24 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX8M-schematic-design/m-p/767361#M119171</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2018-04-25T06:42:24Z</dc:date>
    </item>
    <item>
      <title>Re: Question, i.MX8M schematic design</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX8M-schematic-design/m-p/767362#M119172</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi &lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/Yuri"&gt;Yuri&lt;/A&gt;‌&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks for your support, but this is final confirmation.&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;We cannot find the description of PCIE_RXN_P/N in your &lt;SPAN style="font-size: 10.5pt;"&gt;Hardware Developer’s Guide’(IMX8MDQLQHDG,Rev.0)&lt;/SPAN&gt;.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Can I understand that this is just an omission?&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Best Regards,&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;SPAN&gt;Miyamoto&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 27 Apr 2018 01:23:58 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX8M-schematic-design/m-p/767362#M119172</guid>
      <dc:creator>SLICE</dc:creator>
      <dc:date>2018-04-27T01:23:58Z</dc:date>
    </item>
    <item>
      <title>Re: Question, i.MX8M schematic design</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX8M-schematic-design/m-p/767363#M119173</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; Yes,&amp;nbsp;&lt;SPAN style="color: #51626f; background-color: #ffffff;"&gt;just an omission.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Yuri,&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 27 Apr 2018 03:19:28 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX8M-schematic-design/m-p/767363#M119173</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2018-04-27T03:19:28Z</dc:date>
    </item>
    <item>
      <title>Re: Question, i.MX8M schematic design</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX8M-schematic-design/m-p/767364#M119174</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi &lt;A class="jx-jive-macro-user" href="https://community.nxp.com/people/Yuri"&gt;Yuri&lt;/A&gt;‌&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Noted with thanks !&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;BR,&lt;/P&gt;&lt;P&gt;Miyamoto&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 27 Apr 2018 03:26:16 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Question-i-MX8M-schematic-design/m-p/767364#M119174</guid>
      <dc:creator>SLICE</dc:creator>
      <dc:date>2018-04-27T03:26:16Z</dc:date>
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