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    <title>topic Re: Multiple SDRAM chip support in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Multiple-SDRAM-chip-support/m-p/766969#M119108</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; According to i.MX RT1050 Reference Manual its memory controller SEMC supports&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;SDRAM interface with the following features:&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;• 8/16 bit modes;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;• Up to 512Mb per each Chip Select (CS) and up to 4 CS.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 19 Mar 2018 09:08:43 GMT</pubDate>
    <dc:creator>Yuri</dc:creator>
    <dc:date>2018-03-19T09:08:43Z</dc:date>
    <item>
      <title>Multiple SDRAM chip support</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Multiple-SDRAM-chip-support/m-p/766968#M119107</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Can multiple SDRAM chips be added to the RT1050 (eg:&amp;nbsp;MIMXRT1051DVL6A) external memory interface to expand the amount of addressable RAM? For my application I am needing at least 64MB of RAM and to make this cost effective is seems 2 x 32MB (16MB x 16 bit width) chips would be best.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;From the datasheet it seems possible using multiple CS line but the following statement from a supporting&amp;nbsp;RT1050 introduction slide deck (page 17 -&amp;nbsp;&lt;A class="link-titled" href="https://www.nxp.com/docs/en/supporting-information/i.MX-RT1050-Supporting-Inf.pdf" title="https://www.nxp.com/docs/en/supporting-information/i.MX-RT1050-Supporting-Inf.pdf"&gt;https://www.nxp.com/docs/en/supporting-information/i.MX-RT1050-Supporting-Inf.pdf&lt;/A&gt;) seems to indicate support for only a single 16 bit width DRAM is possible.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;&lt;EM&gt;"Support single x16 DRAM chip or dual x8 DRAM chip"&amp;nbsp;&lt;/EM&gt;&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;Just needing to confirm I can achieve 64MB (or even 96MB) of extern SDRAM on this platform.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;&lt;/STRONG&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 16 Mar 2018 23:36:03 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Multiple-SDRAM-chip-support/m-p/766968#M119107</guid>
      <dc:creator>paulnichols</dc:creator>
      <dc:date>2018-03-16T23:36:03Z</dc:date>
    </item>
    <item>
      <title>Re: Multiple SDRAM chip support</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Multiple-SDRAM-chip-support/m-p/766969#M119108</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; According to i.MX RT1050 Reference Manual its memory controller SEMC supports&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;SDRAM interface with the following features:&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;• 8/16 bit modes;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;• Up to 512Mb per each Chip Select (CS) and up to 4 CS.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;BR /&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 19 Mar 2018 09:08:43 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Multiple-SDRAM-chip-support/m-p/766969#M119108</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2018-03-19T09:08:43Z</dc:date>
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