i.MX ProcessorsのトピックHow to solve timing margin issues from fabrication side in custom hardware design ?

How to solve timing margin issues from fabrication side in custom hardware design ?

peteramond — Wed, 04 Apr 2018 11:09:40 GMT

Hi All,

This is regarding i.MAX6Q based custom hardware design and I'm having timing margin issues in I/O interface between chipset and dram. If I/O interface margin is poor by routing issue or layout, it may cause failure depending on noise pattern ( different application make different noise level). So to solve this issue what do you suggest ?

1) Can we do this using chipset design option to control this kind of timing like phase shift for tDQS and tDQ.? Can you explain how to do this ?

2) Is it possible to down operating frequency ( ex 2400Mbps --> 2133Mbps ) How can we do this in uboot level ?

3) If it is related to clock timing, We can add capacitance or change termination resistance on CLK and CLK/. To do this what we should do ? Which parameter should I change in DDR initialization script before do memory calibration ?

Regards,

Peter.

Re: How to solve timing margin issues from fabrication side in custom hardware design ?

igorpadykov — Wed, 04 Apr 2018 23:37:14 GMT

Hi Peter

1.3. please look on AN4467 i.MX 6 Series DDR Calibration

https://www.nxp.com/docs/en/application-note/AN4467.pdf

2. for changing frequency examples one can look at linux cpufreq, bus drivers described in

Chapter 23 CPU Frequency Scaling (CPUFREQ) Driver, Chapter 24 Dynamic Bus Frequency Driver

attached Linux Manual. For boot with lower frequencies one can use BT_FREQ=1 option

described in Table 8-4. Normal frequency clocks configuration i.MX6DQ Reference Manual

https://www.nxp.com/docs/en/reference-manual/IMX6DQRM.pdf

Best regards
igor
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Re: How to solve timing margin issues from fabrication side in custom hardware design ?

peteramond — Thu, 05 Apr 2018 07:50:20 GMT

Hi igorpadykov

How can I change BT_FREQ=1 value ? Is that in U-boot DCD configuration files ? Could you please tell me the method ?

Regards,

Peter.

Re: How to solve timing margin issues from fabrication side in custom hardware design ?

igorpadykov — Thu, 05 Apr 2018 08:42:49 GMT

Hi Peter

please look at BT_FREQ (BOOT_CFG3[2]) description in

Table 8-2. Boot eFUSE descriptions, Table 8-3. GPIO override contact assignments

i.MX6DQ Reference Manual.

Best regards
igor