i.MX Processors中的主题 Re: AC timing of IPUx_CSI input signals.

AC timing of IPUx_CSI input signals.

takayuki_ishii — Mon, 29 Jan 2018 08:22:17 GMT

hello community,

I have some questions about AC timing of IPUx_CSI signals.

In datashee of i.MX6DQAEC, it have a timing characteristics of IPU CLK and DATA.

Which is a correct answer to major a each parameters.

1) Is start point of Tsu

1-1) center of the IPU_CSI_DATA signal? (OVDD*0.5)

1-2) Vih or Vil of the IPU_CSI_DATA signal? (OVDD*0.7) or (OVDD*0.3)

2) Is end of Tsu

2-1) center of the IPU_CSI_CLK signal? (OVDD*0.5)

2-2) Vih or Vil of the IPU_CSI_CLK signal? (OVDD*0.7) or (OVDD*0.3)

3) Is start point of Thd

3-1) center of the IPU_CSI_CLK signal? (OVDD*0.5)

3-2) Vih or Vil of the IPU_CSI_CLK signal? (OVDD*0.7) or (OVDD*0.3)

4) Is end point of Thd

3-1) center of the IPU_CSI_DATA signal? (OVDD*0.5)

3-2) Vih or Vil of the IPU_CSI_DATA signal? (OVDD*0.7) or (OVDD*0.3)

I am looking forward to hearing from you.

Best regards,

Ishii.

Re: AC timing of IPUx_CSI input signals.

joanxie — Wed, 07 Feb 2018 08:39:36 GMT

refer to the figure, tsu starts valid data signal, end referenced from a low-to-high transition of the pixel clock for 2:1, for CSI should be different mode, like gated mode, non-gated mode, for different mode, one can refer to the Reference Manual to get detailed information.

Re: AC timing of IPUx_CSI input signals.

takayuki_ishii — Thu, 08 Feb 2018 13:31:57 GMT

Hello Joan,

Thank you for your response.

I will refer the Reference Manual to understand a detail of each mode.

Best regards,

Ishii.