topic Re: DDR3 SDRAM ODT setting in i.MX Processors

DDR3 SDRAM ODT setting

ko-hey — Fri, 16 Mar 2018 01:58:06 GMT

Hi all

Let me confirm about ODT setting of following signals.

DRAM_ADDR[15:0]

DRAM_CAS

DRAM_CS0[1:0]

DRAM_DQM[7:0]

DRAM_ODT[1:0]

DRAM_RAS

DRAM_SDBA[2:0]

DRAM_SDCKE[1:0]

DRAM_SDCLK[1:0]_N

DRAM_SDCLK[1:0]_P

DRAM_SDWE

i.MX6 is output, but in the PAD setting register (IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00, ...) of each of them, the 3 bits of the field 10: 8 are ODT setting.

(1) Since i.MX 6 side is output, so the ODT settings is disabled. Am I correct ?

(2)i.MX 6 is output but when ODT setting is set to Disable:
(2-1)

Is this setting effective?
In other words, is the terminating resistor actually connected inside the i.MX6 ?
(2-2)

If it is effective, if choosing an appropriate setting value will it help to improve the quality of the signal?

Ko-hey

Re: DDR3 SDRAM ODT setting

Yuri — Fri, 16 Mar 2018 06:56:06 GMT

Hello,

You are right, termination is provided on receiver side.

So, for read (by CPU) operation (ODT) resistors are provided (if configured) by the CPU on CPU side

(internally). For write - the CPU asserts ODT signal to inform DRAM that memory should provide termination.

It is recommended to use only MMDC_MPODTCTRL register to configure MMDC ODT of i.MX6.

Have a great day,

Yuri

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Re: DDR3 SDRAM ODT setting

ko-hey — Mon, 19 Mar 2018 03:00:28 GMT

Hi YuriMuhin_ng‌

Let me confirm your answer.

Q1'.

I understand that ODT setting is disabled when i.MX6 operates as a output.

So user should set IOMUXC_SW_PAD_CTL_PAD_DRAM_xxx to "000" and set MMDCx_MPODTCTRL as user want.

Am I correcr ?

Q2'.

As you mentioned, ODT setting is disabled when i.MX6 operates as a output.

If user set IOMUXC_SW_PAD_CTL_PAD_DRAM_xxx to other than "000" when i.MX6 operates as a output, the setting isn't valid.

Am I correct ?

Q3.

If Q2' is correct, it is not effective for improving the signal quality.

Am I correct ?

Ko-hey

Re: DDR3 SDRAM ODT setting

ko-hey — Thu, 22 Mar 2018 00:08:21 GMT

Hi YuriMuhin_ng‌

Could you teach me whether the above question is correct or not ?

Ko-hey

Re: DDR3 SDRAM ODT setting

Yuri — Mon, 26 Mar 2018 02:59:05 GMT

Hello,

MMDCx_MPODTCTRL (group) settings have higher priority.

Regards,

Yuri.

Re: DDR3 SDRAM ODT setting

ko-hey — Thu, 29 Mar 2018 07:20:41 GMT

Hi YuriMuhin_ng‌

I understand it's higher priority.

In that case, why does IOMUXC_SW_PAD_CTL_PAD_DRAM_xxx have the ODT setting field ?

Do you have any reason ?

Furthermore, is there any bad impact when user set except for "disabled" ?

Ko-hey

Re: DDR3 SDRAM ODT setting

Yuri — Thu, 29 Mar 2018 07:48:19 GMT

Hello,

It is possible to configure each pin separately, but group setting are more convenient.

Regards,

Yuri.

Re: DDR3 SDRAM ODT setting

ko-hey — Thu, 29 Mar 2018 08:13:52 GMT

Is there no bad impact to configure each pin separately ?

Am I correct ?

Ko-hey

Re: DDR3 SDRAM ODT setting

Yuri — Thu, 29 Mar 2018 08:44:22 GMT

Yes, correct.