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    <title>topic Re: Problem of chip boot in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Problem-of-chip-boot/m-p/759110#M118046</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp;Generally, violation of&amp;nbsp; i.MX6 specs, provided in Datasheet(s), may cause improper&lt;/P&gt;&lt;P&gt;fuse burning, but I never heard about it before. Perhaps it makes sense to check the issue&lt;/P&gt;&lt;P&gt;with distributor.&amp;nbsp; &amp;nbsp;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Yuri.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 07 Dec 2017 03:59:14 GMT</pubDate>
    <dc:creator>Yuri</dc:creator>
    <dc:date>2017-12-07T03:59:14Z</dc:date>
    <item>
      <title>Problem of chip boot</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Problem-of-chip-boot/m-p/759104#M118040</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;I produced 90 pieces of boards in batch, of which 87 had problems and 3 were normal. The problematic CPU is :MCIMX6D5EYM10AD &amp;nbsp; Notice this:QAM1535 &amp;nbsp;&amp;nbsp;but 3 pieces of good CPU MARK :QAM1646.&lt;/P&gt;&lt;P&gt;87 pieces can be downloaded normally, but can't start。&amp;nbsp;There is no data in the serial port。The appendage is the normal boot and the abnormal boot information。&lt;SPAN&gt;3 pieces of good board are normal 。Is there a difference in the curing of the guide ROM?Can you tell me how to deal with it?The boot mode of the board is eMMC, and the peripheral CFG bits are all normal。&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sat, 02 Dec 2017 06:11:55 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Problem-of-chip-boot/m-p/759104#M118040</guid>
      <dc:creator>jhp</dc:creator>
      <dc:date>2017-12-02T06:11:55Z</dc:date>
    </item>
    <item>
      <title>Re: Problem of chip boot</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Problem-of-chip-boot/m-p/759105#M118041</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; Have You tried the DDR Stress test ?&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/docs/DOC-105652"&gt;https://community.nxp.com/docs/DOC-105652&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; Also, You may run the Stress test just after boot crash in order &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;to check boot options, shown in test log as SRC_SBMR1 and &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;SRC_SBMR2 registers).&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 05 Dec 2017 04:42:32 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Problem-of-chip-boot/m-p/759105#M118041</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2017-12-05T04:42:32Z</dc:date>
    </item>
    <item>
      <title>Re: Problem of chip boot</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Problem-of-chip-boot/m-p/759106#M118042</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thank you for your reply. I and my team have been working hard to find the problem, and finally found that the 87 CPU BT_FUSE_SEL Value bits that have a problem have been set 1,ONLY BOOT FROM eFUSEs SETTING, such as Figure 1. Figure 2 is what we tried to modify, but it was not successful. Looking for similar information on the Internet, people give the conclusion that they can only burn and write once and can't be modified. The actual test is true. Can you tell me a clear statement? Is there a way to unlock the status?&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="bit_fuse.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/57887i361505D66A9A2362/image-size/large?v=v2&amp;amp;px=999" role="button" title="bit_fuse.png" alt="bit_fuse.png" /&gt;&lt;/span&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="BIT2.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/57947iAFFC35CDB34254D9/image-size/large?v=v2&amp;amp;px=999" role="button" title="BIT2.png" alt="BIT2.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 05 Dec 2017 05:00:03 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Problem-of-chip-boot/m-p/759106#M118042</guid>
      <dc:creator>jhp</dc:creator>
      <dc:date>2017-12-05T05:00:03Z</dc:date>
    </item>
    <item>
      <title>Re: Problem of chip boot</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Problem-of-chip-boot/m-p/759107#M118043</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; The fuses are really once programmed.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Yuri.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 05 Dec 2017 08:46:55 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Problem-of-chip-boot/m-p/759107#M118043</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2017-12-05T08:46:55Z</dc:date>
    </item>
    <item>
      <title>Re: Problem of chip boot</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Problem-of-chip-boot/m-p/759108#M118044</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thank you for your reply. We have changed the new batch of CPU to solve this problem. Thank you very much!&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 07 Dec 2017 00:54:51 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Problem-of-chip-boot/m-p/759108#M118044</guid>
      <dc:creator>jhp</dc:creator>
      <dc:date>2017-12-07T00:54:51Z</dc:date>
    </item>
    <item>
      <title>Re: Problem of chip boot</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Problem-of-chip-boot/m-p/759109#M118045</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;One thing that does not understand is why the purchase of CPU has such a problem, is it a custom version of a new product that has been used or a custom version of a NXP original large customer? I don't know if there is any of the latter. At present, the positioning is the problem of CPU incoming material.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 07 Dec 2017 01:01:40 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Problem-of-chip-boot/m-p/759109#M118045</guid>
      <dc:creator>jhp</dc:creator>
      <dc:date>2017-12-07T01:01:40Z</dc:date>
    </item>
    <item>
      <title>Re: Problem of chip boot</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Problem-of-chip-boot/m-p/759110#M118046</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp; &amp;nbsp;Generally, violation of&amp;nbsp; i.MX6 specs, provided in Datasheet(s), may cause improper&lt;/P&gt;&lt;P&gt;fuse burning, but I never heard about it before. Perhaps it makes sense to check the issue&lt;/P&gt;&lt;P&gt;with distributor.&amp;nbsp; &amp;nbsp;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Yuri.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 07 Dec 2017 03:59:14 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Problem-of-chip-boot/m-p/759110#M118046</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2017-12-07T03:59:14Z</dc:date>
    </item>
    <item>
      <title>Re: Problem of chip boot</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Problem-of-chip-boot/m-p/759111#M118047</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Ok，I see.Thanks a lot.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 07 Dec 2017 04:19:03 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Problem-of-chip-boot/m-p/759111#M118047</guid>
      <dc:creator>jhp</dc:creator>
      <dc:date>2017-12-07T04:19:03Z</dc:date>
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