i.MX ProcessorsのトピックRe: about i.MX6 PCIe cache coherency

about i.MX6 PCIe cache coherency

masamiyasui — Thu, 09 Nov 2017 02:10:17 GMT

In i.MX6Q PCIe End Point, if cache is enabled in the inbound area, I think that cache invalidate is necessary before and after writing from Root Complex to this area.
How can End Point know the timing of these cache invalidate?

Without these cache invalidate, End Point could not read the data which Root Complex wrote to this area.

Re: about i.MX6 PCIe cache coherency

Yuri — Thu, 09 Nov 2017 03:58:43 GMT

Hello,

I.MX6 does not support cache coherency (in hardware). Therefore it

may be recommended to configure the PCIe memory area as non-cached,

if several bus masters can access it.

Have a great day,
Yuri

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Re: about i.MX6 PCIe cache coherency

masamiyasui — Thu, 09 Nov 2017 05:06:20 GMT

Thank you very much for your quick response.