Starting kernel ... using 4 seconds to start unpress kernel

jiujinhong — Tue, 02 Jan 2018 10:11:12 GMT

Hi,

The issue is that 4.1.15 BSP starting kernel ... using 4 seconds to start to Uncompressing Linux. After enable EARLY_PRINTK, it will hang in below case.

20180102_14:49:26]
20180102_14:49:26]Starting kernel ...
20180102_14:49:26]
20180102_14:49:26]Uncompressing Linux... done, booting the kernel.
20180102_14:49:26]Booting Linux on physical CPU 0x0
20180102_14:49:26]Initializing cgroup subsys cpu
20180102_14:49:26]Initializing cgroup subsys cpuacct
20180102_14:49:26]Linux version 4.1.15 (jiujin@jiujin-linux) (gcc version 4.9 20150123 (prerelease) (GCC) ) #114 SMP PREEMPT Tue Jan 2 14:13:17 CST 2018
20180102_14:49:26]CPU: ARMv7 Processor [412fc09a] revision 10 (ARMv7), cr=10c53c7d
20180102_14:49:26]CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache
20180102_14:49:26]Machine model: Freescale i.MX6 Quad SABRE Smart Device Board
20180102_14:49:26][    0.000000] Booting Linux on physical CPU 0x0
20180102_14:49:26][    0.000000] Initializing cgroup subsys cpu
20180102_14:49:26][    0.000000] Initializing cgroup subsys cpuacct
20180102_14:49:26][    0.000000] Linux version 4.1.15 (jiujin@jiujin-linux) (gcc version 4.9 20150123 (prerelease) (GCC) ) #114 SMP PREEMPT Tue Jan 2 14:13:17 CST 2018
20180102_14:49:26][    0.000000] CPU: ARMv7 Processor [412fc09a] revision 10 (ARMv7), cr=10c53c7d
20180102_14:49:27][    0.000000] CPU: PIPT / VIPT no

---> enable EARLY_PRINTK support, hangs here.

Re: Starting kernel ... using 4 seconds to start unpress kernel

igorpadykov — Wed, 03 Jan 2018 07:14:58 GMT

Hi jiu

what bsp used in the case, please try with demo image

https://www.nxp.com/webapp/Download?colCode=L4.1.15_2.0.0_MX6QDLSOLO&appType=license&location=null

for debugging one van try AN4553 Using Open Source Debugging Tools for Linux on i.MX Processors
https://www.nxp.com/docs/en/application-note/AN4553.pdf

Best regards
igor
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Re: Starting kernel ... using 4 seconds to start unpress kernel

jiujinhong — Thu, 11 Jan 2018 07:15:14 GMT

From 2e2f1168059373faf020fb882f3c4d65a5f40c45 Mon Sep 17 00:00:00 2001
From: hongjiujin <hongjiujin@xxx.com>
Date: Thu, 11 Jan 2018 14:04:23 +0800
Subject: [PATCH] linux kernel: support early console and fix mistakes in
includes/dts

Register early console so that kernel can quickly startup.
It can speedup almost 2~3 seconds between "Starting kernel..." and "Uncompressing".

Signed-off-by: hongjiujin <hongjiujin@xxx.com>
---
.../uboot-imx/include/configs/mx6sabre_common.h    |   2 +-
.../uboot-imx/include/configs/mx6sabresd.h         |   2 +-
device/fsl/sabresd_6dq/BoardConfig.mk              |   2 +-
kernel_imx/arch/arm/boot/dts/imx6qdl-sabresd.dtsi |   4 +-
kernel_imx/arch/arm/mach-imx/mach-imx6q.c          | 26 ++
kernel_imx/drivers/tty/serial/Makefile             |   1 +
kernel_imx/drivers/tty/serial/mxc_uart_early.c     | 188 +++++++++++++++
kernel_imx/drivers/tty/serial/mxc_uart_early.h     | 267 +++++++++++++++++++++
8 files changed, 487 insertions(+), 5 deletions(-)
create mode 100644 kernel_imx/drivers/tty/serial/mxc_uart_early.c
create mode 100755 kernel_imx/drivers/tty/serial/mxc_uart_early.h

diff --git a/bootable/bootloader/uboot-imx/include/configs/mx6sabre_common.h b/bootable/bootloader/uboot-imx/include/configs/mx6sabre_common.h
index bf30c62..bd062e3 100644
--- a/bootable/bootloader/uboot-imx/include/configs/mx6sabre_common.h
+++ b/bootable/bootloader/uboot-imx/include/configs/mx6sabre_common.h
@@ -90,7 +90,7 @@

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
-#define CONFIG_CONS_INDEX              1
+#define CONFIG_CONS_INDEX              4       /* UART4 */
#define CONFIG_BAUDRATE                        115200

/* Command definition */
diff --git a/bootable/bootloader/uboot-imx/include/configs/mx6sabresd.h b/bootable/bootloader/uboot-imx/include/configs/mx6sabresd.h
index 14f1ce3..cd84c29 100755
--- a/bootable/bootloader/uboot-imx/include/configs/mx6sabresd.h
+++ b/bootable/bootloader/uboot-imx/include/configs/mx6sabresd.h
@@ -27,7 +27,7 @@
#define PHYS_SDRAM_SIZE       (1u * 1024 * 1024 * 1024)
#elif defined(CONFIG_MX6Q)
#define CONFIG_DEFAULT_FDT_FILE   "imx6q-sabresd.dtb"
-#define PHYS_SDRAM_SIZE       (1u * 1024 * 1024 * 1024)
+#define PHYS_SDRAM_SIZE       (2u * 1024 * 1024 * 1024)
#elif defined(CONFIG_MX6DL)
#define CONFIG_DEFAULT_FDT_FILE   "imx6dl-sabresd.dtb"
#define PHYS_SDRAM_SIZE       (1u * 1024 * 1024 * 1024)
diff --git a/device/fsl/sabresd_6dq/BoardConfig.mk b/device/fsl/sabresd_6dq/BoardConfig.mk
index 8fd07e7..cd63be7 100755
--- a/device/fsl/sabresd_6dq/BoardConfig.mk
+++ b/device/fsl/sabresd_6dq/BoardConfig.mk
@@ -109,7 +109,7 @@ $(error "TARGET_USERIMAGES_USE_UBIFS and TARGET_USERIMAGES_USE_EXT4 config open
endif
endif

-BOARD_KERNEL_CMDLINE := console=ttymxc3,115200 init=/init video=mxcfb0:dev=ldb,bpp=32 video=mxcfb1:off video=mxcfb2:off video=mxcfb3:off vmalloc=128M androidboot.console=ttymxc3 consoleblank=0 androidboot.hardware=freescale cma=448M androidboot.selinux=permissive androidboot.dm_verity=disabled loglevel=8 ldo_active=on
+BOARD_KERNEL_CMDLINE := consol=mxcuart,0x21f0000,115200n8 console=ttymxc3,115200 init=/init video=mxcfb0:dev=ldb,bpp=32 video=mxcfb1:off vmalloc=128M androidboot.console=ttymxc3 consoleblank=0 androidboot.hardware=freescale cma=448M androidboot.selinux=permissive androidboot.dm_verity=disabled loglevel=8

ifeq ($(TARGET_USERIMAGES_USE_UBIFS),true)
#UBI boot command line.
diff --git a/kernel_imx/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/kernel_imx/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index 91d29a0..67a85e8 100755
--- a/kernel_imx/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/kernel_imx/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -33,7 +33,7 @@
    };

    chosen {
-       stdout-path = &uart1;
+       stdout-path = &uart4;
    };

    leds {
@@ -47,7 +47,7 @@
    };

    memory: memory {
-       reg = <0x10000000 0x40000000>;
+       reg = <0x10000000 0x80000000>;
    };

    regulators {
diff --git a/kernel_imx/arch/arm/mach-imx/mach-imx6q.c b/kernel_imx/arch/arm/mach-imx/mach-imx6q.c
index 92f8e84..4ad5e1b 100644
--- a/kernel_imx/arch/arm/mach-imx/mach-imx6q.c
+++ b/kernel_imx/arch/arm/mach-imx/mach-imx6q.c
@@ -196,6 +196,31 @@ static void __init imx6q_enet_phy_init(void)
    }
}

+extern int mxc_early_serial_console_init(unsigned long base, struct clk *clk);
+#define MX6Q_UART4_BASE 0x21f0000
+static void __init imx6q_early_serialcon_setup(void)
+{
+   struct device_node *np;
+   struct clk *uart_clk;
+
+   np = of_find_compatible_node(NULL, NULL, "fsl,imx6q-uart");
+   if (!np) {
+       pr_warn("%s: failed to find uart node\n", __func__);
+       return;
+   }
+
+   uart_clk = of_clk_get_by_name(np, "ipg");
+   if (IS_ERR(uart_clk)) {
+       pr_warn("%s: failed to get uart clock\n", __func__);
+       goto put_node;
+   }
+
+   mxc_early_serial_console_init(MX6Q_UART4_BASE, uart_clk);
+
+put_node:
+   of_node_put(np);
+}
+
static void __init imx6q_1588_init(void)
{
    struct device_node *np;
@@ -353,6 +378,7 @@ static void __init imx6q_init_machine(void)

    of_platform_populate(NULL, of_default_bus_match_table, NULL, parent);

+   imx6q_early_serialcon_setup();
    imx6q_enet_init();
    imx_anatop_init();
    imx6q_csi_mux_init();
diff --git a/kernel_imx/drivers/tty/serial/Makefile b/kernel_imx/drivers/tty/serial/Makefile
index c3ac3d9..ed563d1 100644
--- a/kernel_imx/drivers/tty/serial/Makefile
+++ b/kernel_imx/drivers/tty/serial/Makefile
@@ -44,6 +44,7 @@ obj-$(CONFIG_SERIAL_SH_SCI) += sh-sci.o
obj-$(CONFIG_SERIAL_SGI_L1_CONSOLE) += sn_console.o
obj-$(CONFIG_SERIAL_CPM) += cpm_uart/
obj-$(CONFIG_SERIAL_IMX) += imx.o
+obj-$(CONFIG_SERIAL_IMX_CONSOLE) += mxc_uart_early.o
obj-$(CONFIG_SERIAL_MPC52xx) += mpc52xx_uart.o
obj-$(CONFIG_SERIAL_ICOM) += icom.o
obj-$(CONFIG_SERIAL_M32R_SIO) += m32r_sio.o
diff --git a/kernel_imx/drivers/tty/serial/mxc_uart_early.c b/kernel_imx/drivers/tty/serial/mxc_uart_early.c
new file mode 100644
index 0000000..77eb9e2
--- /dev/null
+++ b/kernel_imx/drivers/tty/serial/mxc_uart_early.c
@@ -0,0 +1,188 @@
+/*
+ * Copyright (C) 2011-2012 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+/*!
+ * @file drivers/serial/mxc_uart_early.c
+ *
+ * @brief Driver for the Freescale Semiconductor MXC serial ports based on
+ * drivers/char/8250_early.c,
+ * Copyright 2004 Hewlett-Packard Development Company,
+ * L.P.by Bjorn Helgaasby.
+ *
+ * Early serial console for MXC UARTS.
+ *
+ * This is for use before the serial driver has initialized, in
+ * particular, before the UARTs have been discovered and named.
+ * Instead of specifying the console device as, e.g., "ttymxc0",
+ * we locate the device directly by its MMIO or I/O port address.
+ *
+ * The user can specify the device directly, e.g.,
+ *   console=mxcuart,0x43f90000,115200n8
+ * or platform code can call early_uart_console_init() to set
+ * the early UART device.
+ *
+ * After the normal serial driver starts, we try to locate the
+ * matching ttymxc device and start a console there.
+ */
+
+/*
+ * Include Files
+ */
+
+#include <linux/tty.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/console.h>
+#include <linux/serial_core.h>
+#include <linux/serial_reg.h>
+#include <linux/clk.h>
+
+#include "mxc_uart_early.h"
+
+struct mxc_early_uart_device {
+   struct uart_port port;
+   char options[16];   /* e.g., 115200n8 */
+   unsigned int baud;
+   struct clk *clk;
+};
+static struct mxc_early_uart_device mxc_early_device __initdata;
+
+/*
+ * Write out a character once the UART is ready
+ */
+static void __init mxcuart_console_write_char(struct uart_port *port, int ch)
+{
+   unsigned int status;
+
+   do {
+       status = readl(port->membase + MXC_UARTUSR2);
+   } while ((status & MXC_UARTUSR2_TXFE) == 0);
+   writel(ch, port->membase + MXC_UARTUTXD);
+}
+
+/*!
+ * This function is called to write the console messages through the UART port.
+ *
+ * @param   co    the console structure
+ * @param   s     the log message to be written to the UART
+ * @param   count length of the message
+ */
+void __init early_mxcuart_console_write(struct console *co, const char *s,
+                   u_int count)
+{
+   struct uart_port *port = &mxc_early_device.port;
+   unsigned int status, oldcr1, oldcr2, oldcr3, cr2, cr3;
+
+   /*
+   * First save the control registers and then disable the interrupts
+   */
+   oldcr1 = readl(port->membase + MXC_UARTUCR1);
+   oldcr2 = readl(port->membase + MXC_UARTUCR2);
+   oldcr3 = readl(port->membase + MXC_UARTUCR3);
+   cr2 =
+        oldcr2 & ~(MXC_UARTUCR2_ATEN | MXC_UARTUCR2_RTSEN |
+               MXC_UARTUCR2_ESCI);
+   cr3 =
+        oldcr3 & ~(MXC_UARTUCR3_DCD | MXC_UARTUCR3_RI |
+               MXC_UARTUCR3_DTRDEN);
+   writel(MXC_UARTUCR1_UARTEN, port->membase + MXC_UARTUCR1);
+   writel(cr2, port->membase + MXC_UARTUCR2);
+   writel(cr3, port->membase + MXC_UARTUCR3);
+
+   /* Transmit string */
+   uart_console_write(port, s, count, mxcuart_console_write_char);
+
+   /*
+   * Finally, wait for the transmitter to become empty
+   */
+   do {
+       status = readl(port->membase + MXC_UARTUSR2);
+   } while (!(status & MXC_UARTUSR2_TXDC));
+
+   /*
+   * Restore the control registers
+   */
+   writel(oldcr1, port->membase + MXC_UARTUCR1);
+   writel(oldcr2, port->membase + MXC_UARTUCR2);
+   writel(oldcr3, port->membase + MXC_UARTUCR3);
+}
+
+static unsigned int __init probe_baud(struct uart_port *port)
+{
+   /* FIXME Return Default Baud Rate */
+   return 115200;
+}
+
+static int __init mxc_early_uart_setup(struct console *console, char *options)
+{
+   struct mxc_early_uart_device *device = &mxc_early_device;
+   struct uart_port *port = &device->port;
+   int length;
+
+   if (device->port.membase || device->port.iobase)
+       return -ENODEV;
+
+   port->uartclk = 5600000;
+   port->iotype = UPIO_MEM;
+   port->membase = ioremap(port->mapbase, SZ_4K);
+
+   if (options) {
+       device->baud = simple_strtoul(options, NULL, 0);
+       length = min(strlen(options), sizeof(device->options));
+       strncpy(device->options, options, length);
+   } else {
+       device->baud = probe_baud(port);
+       snprintf(device->options, sizeof(device->options), "%u",
+           device->baud);
+   }
+   printk(KERN_INFO
+           "MXC_Early serial console at MMIO 0x%x (options '%s')\n",
+           port->mapbase, device->options);
+   return 0;
+}
+
+static struct console mxc_early_uart_console __initdata = {
+   .name = "ttymxc",
+   .write = early_mxcuart_console_write,
+   .setup = mxc_early_uart_setup,
+   .flags = CON_PRINTBUFFER | CON_BOOT,
+   .index = -1,
+};
+
+int __init mxc_early_serial_console_init(unsigned long base, struct clk *clk)
+{
+   mxc_early_device.clk = clk;
+   mxc_early_device.port.mapbase = base;
+
+   register_console(&mxc_early_uart_console);
+   return 0;
+}
+
+int __init mxc_early_uart_console_disable(void)
+{
+   struct mxc_early_uart_device *device = &mxc_early_device;
+   struct uart_port *port = &device->port;
+
+   if (mxc_early_uart_console.index >= 0) {
+       unregister_console(&mxc_early_uart_console);
+       iounmap(port->membase);
+       clk_put(device->clk);
+   }
+   return 0;
+}
+late_initcall_sync(mxc_early_uart_console_disable);
diff --git a/kernel_imx/drivers/tty/serial/mxc_uart_early.h b/kernel_imx/drivers/tty/serial/mxc_uart_early.h
new file mode 100755
index 0000000..689aaad
--- /dev/null
+++ b/kernel_imx/drivers/tty/serial/mxc_uart_early.h
@@ -0,0 +1,267 @@
+/*
+ * Copyright 2004-2011 Freescale Semiconductor, Inc. All Rights Reserved.
+ */
+
+/*
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+/*!
+ * @defgroup UART Universal Asynchronous Receiver Transmitter (UART) Driver
+ */
+
+/*!
+ * @file arch-mxc/mxc_uart.h
+ *
+ * @brief This file contains the UART configuration structure definition.
+ *
+ *
+ * @ingroup UART
+ */
+
+#ifndef __ASM_ARCH_MXC_UART_H__
+#define __ASM_ARCH_MXC_UART_H__
+
+#ifdef __KERNEL__
+
+#include <linux/serial_core.h>
+
+/*
+ * The modes of the UART ports
+ */
+#define MODE_DTE                0
+#define MODE_DCE                1
+/*
+ * Is the UART configured to be a IR port
+ */
+#define IRDA                    0
+#define NO_IRDA                 1
+
+/*!
+ * This structure is used to store the the physical and virtual
+ * addresses of the UART DMA receive buffer.
+ */
+typedef struct {
+   /*!
+   * DMA Receive buffer virtual address
+   */
+   char *rx_buf;
+   /*!
+   * DMA Receive buffer physical address
+   */
+   dma_addr_t rx_handle;
+} mxc_uart_rxdmamap;
+
+/*!
+ * This structure is a way for the low level driver to define their own
+ * \b uart_port structure. This structure includes the core \b uart_port
+ * structure that is provided by Linux as an element and has other
+ * elements that are specifically required by this low-level driver.
+ */
+typedef struct {
+   /*!
+   * The port structure holds all the information about the UART
+   * port like base address, and so on.
+   */
+   struct uart_port port;
+   /*!
+   * Flag to determine if the interrupts are muxed.
+   */
+   int ints_muxed;
+   /*!
+   * Array that holds the receive and master interrupt numbers
+   * when the interrupts are not muxed.
+   */
+   int irqs[2];
+   /*!
+   * Flag to determine the DTE/DCE mode.
+   */
+   int mode;
+   /*!
+   * Flag to hold the IR mode of the port.
+   */
+   int ir_mode;
+   /*!
+   * Flag to enable/disable the UART port.
+   */
+   int enabled;
+   /*!
+   * Flag to indicate if we wish to use hardware-driven hardware
+   * flow control.
+   */
+   int hardware_flow;
+   /*!
+   * Holds the threshold value at which the CTS line is deasserted in
+   * case we use hardware-driven hardware flow control.
+   */
+   unsigned int cts_threshold;
+   /*!
+   * Flag to enable/disable DMA data transfer.
+   */
+   int dma_enabled;
+   /*!
+   * Holds the DMA receive buffer size.
+   */
+   int dma_rxbuf_size;
+   /*!
+   * DMA Receive buffers information
+   */
+   mxc_uart_rxdmamap *rx_dmamap;
+   /*!
+   * DMA RX buffer id
+   */
+   int dma_rxbuf_id;
+   /*!
+   * DMA Transmit buffer virtual address
+   */
+   char *tx_buf;
+   /*!
+   * DMA Transmit buffer physical address
+   */
+   dma_addr_t tx_handle;
+   /*!
+   * Holds the RxFIFO threshold value.
+   */
+   unsigned int rx_threshold;
+   /*!
+   * Holds the TxFIFO threshold value.
+   */
+   unsigned int tx_threshold;
+   /*!
+   * Information whether this is a shared UART
+   */
+   unsigned int shared;
+   /*!
+   * Clock id for UART clock
+   */
+   struct clk *clk;
+   /*!
+   * Information whether RXDMUXSEL must be set or not for IR port
+   */
+   int rxd_mux;
+   int ir_tx_inv;
+   int ir_rx_inv;
+} uart_mxc_port;
+
+/* Address offsets of the UART registers */
+#define MXC_UARTURXD            0x000   /* Receive reg */
+#define MXC_UARTUTXD            0x040   /* Transmitter reg */
+#define   MXC_UARTUCR1            0x080   /* Control reg 1 */
+#define MXC_UARTUCR2            0x084   /* Control reg 2 */
+#define MXC_UARTUCR3            0x088   /* Control reg 3 */
+#define MXC_UARTUCR4            0x08C   /* Control reg 4 */
+#define MXC_UARTUFCR            0x090   /* FIFO control reg */
+#define MXC_UARTUSR1            0x094   /* Status reg 1 */
+#define MXC_UARTUSR2            0x098   /* Status reg 2 */
+#define MXC_UARTUESC            0x09C   /* Escape character reg */
+#define MXC_UARTUTIM            0x0A0   /* Escape timer reg */
+#define MXC_UARTUBIR            0x0A4   /* BRM incremental reg */
+#define MXC_UARTUBMR            0x0A8   /* BRM modulator reg */
+#define MXC_UARTUBRC            0x0AC   /* Baud rate count reg */
+#define MXC_UARTONEMS           0x0B0   /* One millisecond reg */
+#define MXC_UARTUTS             0x0B4   /* Test reg */
+#define MXC_UARTUMCR            0x0B8   /* RS485 Mode control */
+
+/* Bit definations of UCR1 */
+#define MXC_UARTUCR1_ADEN       0x8000
+#define MXC_UARTUCR1_ADBR       0x4000
+#define MXC_UARTUCR1_TRDYEN     0x2000
+#define MXC_UARTUCR1_IDEN       0x1000
+#define MXC_UARTUCR1_RRDYEN     0x0200
+#define MXC_UARTUCR1_RXDMAEN    0x0100
+#define MXC_UARTUCR1_IREN       0x0080
+#define MXC_UARTUCR1_TXMPTYEN   0x0040
+#define MXC_UARTUCR1_RTSDEN     0x0020
+#define MXC_UARTUCR1_SNDBRK     0x0010
+#define MXC_UARTUCR1_TXDMAEN    0x0008
+#define MXC_UARTUCR1_ATDMAEN    0x0004
+#define MXC_UARTUCR1_DOZE       0x0002
+#define MXC_UARTUCR1_UARTEN     0x0001
+
+/* Bit definations of UCR2 */
+#define MXC_UARTUCR2_ESCI       0x8000
+#define MXC_UARTUCR2_IRTS       0x4000
+#define MXC_UARTUCR2_CTSC       0x2000
+#define MXC_UARTUCR2_CTS        0x1000
+#define MXC_UARTUCR2_PREN       0x0100
+#define MXC_UARTUCR2_PROE       0x0080
+#define MXC_UARTUCR2_STPB       0x0040
+#define MXC_UARTUCR2_WS         0x0020
+#define MXC_UARTUCR2_RTSEN      0x0010
+#define MXC_UARTUCR2_ATEN       0x0008
+#define MXC_UARTUCR2_TXEN       0x0004
+#define MXC_UARTUCR2_RXEN       0x0002
+#define MXC_UARTUCR2_SRST       0x0001
+
+/* Bit definations of UCR3 */
+#define MXC_UARTUCR3_DTREN      0x2000
+#define MXC_UARTUCR3_PARERREN   0x1000
+#define MXC_UARTUCR3_FRAERREN   0x0800
+#define MXC_UARTUCR3_DSR        0x0400
+#define MXC_UARTUCR3_DCD        0x0200
+#define MXC_UARTUCR3_RI         0x0100
+#define MXC_UARTUCR3_RXDSEN     0x0040
+#define MXC_UARTUCR3_AWAKEN     0x0010
+#define MXC_UARTUCR3_DTRDEN     0x0008
+#define MXC_UARTUCR3_RXDMUXSEL 0x0004
+#define MXC_UARTUCR3_INVT       0x0002
+
+/* Bit definations of UCR4 */
+#define MXC_UARTUCR4_CTSTL_OFFSET       10
+#define MXC_UARTUCR4_CTSTL_MASK         (0x3F << 10)
+#define MXC_UARTUCR4_INVR               0x0200
+#define MXC_UARTUCR4_ENIRI              0x0100
+#define MXC_UARTUCR4_REF16              0x0040
+#define MXC_UARTUCR4_IRSC               0x0020
+#define MXC_UARTUCR4_TCEN               0x0008
+#define MXC_UARTUCR4_OREN               0x0002
+#define MXC_UARTUCR4_DREN               0x0001
+
+/* Bit definations of UFCR */
+#define MXC_UARTUFCR_RFDIV              0x0200   /* Ref freq div is set to 2 */
+#define MXC_UARTUFCR_RFDIV_OFFSET       7
+#define MXC_UARTUFCR_RFDIV_MASK         (0x7 << 7)
+#define MXC_UARTUFCR_TXTL_OFFSET        10
+#define MXC_UARTUFCR_DCEDTE             0x0040
+
+/* Bit definations of URXD */
+#define MXC_UARTURXD_ERR        0x4000
+#define MXC_UARTURXD_OVRRUN     0x2000
+#define MXC_UARTURXD_FRMERR     0x1000
+#define MXC_UARTURXD_BRK        0x0800
+#define MXC_UARTURXD_PRERR      0x0400
+
+/* Bit definations of USR1 */
+#define MXC_UARTUSR1_PARITYERR 0x8000
+#define MXC_UARTUSR1_RTSS       0x4000
+#define MXC_UARTUSR1_TRDY       0x2000
+#define MXC_UARTUSR1_RTSD       0x1000
+#define MXC_UARTUSR1_FRAMERR    0x0400
+#define MXC_UARTUSR1_RRDY       0x0200
+#define MXC_UARTUSR1_AGTIM      0x0100
+#define MXC_UARTUSR1_DTRD       0x0080
+#define MXC_UARTUSR1_AWAKE      0x0010
+
+/* Bit definations of USR2 */
+#define MXC_UARTUSR2_TXFE       0x4000
+#define MXC_UARTUSR2_IDLE       0x1000
+#define MXC_UARTUSR2_RIDELT     0x0400
+#define MXC_UARTUSR2_RIIN       0x0200
+#define MXC_UARTUSR2_DCDDELT    0x0040
+#define MXC_UARTUSR2_DCDIN      0x0020
+#define MXC_UARTUSR2_TXDC       0x0008
+#define MXC_UARTUSR2_ORE        0x0002
+#define MXC_UARTUSR2_RDR        0x0001
+#define MXC_UARTUSR2_BRCD       0x0004
+
+/* Bit definations of UTS */
+#define MXC_UARTUTS_LOOP        0x1000
+
+#endif               /* __KERNEL__ */
+
+#endif               /* __ASM_ARCH_MXC_UART_H__ */
--
2.7.4

topic Re: Starting kernel ... using 4 seconds to start unpress kernel in i.MX Processors

Starting kernel ... using 4 seconds to start unpress kernel

Re: Starting kernel ... using 4 seconds to start unpress kernel

Re: Starting kernel ... using 4 seconds to start unpress kernel