topic Re: i.MX 7Dual SPL boot in i.MX Processors

i.MX 7Dual SPL boot

urimashiach — Mon, 14 May 2018 14:47:53 GMT

Hello,

We have recently upgraded to i.MX 7Dual MCIMX7D5EVM10SD.

We are not able to boot with SPL U-Boot.

According to the Final Product Change Notification, one of the modification is:

"ROM performance enhancement".

Please provide more details regarding the above modification.

Thanks,

Uri

Re: i.MX 7Dual SPL boot

gusarambula — Wed, 23 May 2018 00:33:54 GMT

Hello Uri,

The change in Silicon Revision 1.3 regarding the ROM enhancement is the addition of a couple of fuses to the fusemap related to the Serial Download Mode. Fuse SDP_DISABLE enables/disables Serial Download mode support. Fuse SDP_READ_ENABLE enables/disables reads using Serial Download mode.

I hope this information helps,

Regards,

Re: i.MX 7Dual SPL boot

urimashiach — Sun, 27 May 2018 13:03:16 GMT

Hello gusarambula,

The problem was solved by increasing the SPL base address by 4 Kbyte.

According to i.MX 7Dual Applications Processor Reference Manual, section 6.6.4.1 (Internal ROM/RAM memory map):

The entire OCRAM region can be used freely after the boot.

In silicon revision 1.3, the SPL is functioning only if loaded 4 Kbyte after the beginning of the OCRAM region.

It seems like the above modification is not documented.

Thanks,

Uri

Re: i.MX 7Dual SPL boot

steveschefterti — Wed, 17 Oct 2018 20:33:04 GMT

Thanks for posting this very useful information Uri. I'll just add that the entirety of SPL must be loaded above 4K after the beginning of OCRAM, not just the code.

The default value for CONFIG_SPL_TEXT_BASE is 0x00911000, which is already 4K into OCRAM. However, the code is preceded by a small header so it is necessary to set CONFIG_SPL_TEXT_BASE to 0x00912000. I had originally thought that the text base had already been bumped by 4K due to the problem that Uri described, but that was not the case.