topic Re: Linux and Bare Metal with shared memory and cache coherency settings? in i.MX Processors

Linux and Bare Metal with shared memory and cache coherency settings?

christoph8446 — Thu, 30 Nov 2017 13:29:10 GMT

Hello,

I want to make a shared memory between linux (core0) and my bare metal (Core1) system. It works if I configure the mmu_map_l1_range in the mmu.c in my bare metal system as noncacheable! If I try to change the settings to kOuterInner_WB_WA and I activated SCU (also on CP15) because I want to use cache coherency it doesn’t work anymore! I only modified the MMU TLB setting on my bare metal system. Do I need to change also settings on the linux side to achieve cache coherency for the shared memory area.

Thank you in advance!

Regards Christoph

Re: Linux and Bare Metal with shared memory and cache coherency settings?

Yuri — Fri, 01 Dec 2017 09:13:16 GMT

Hello,

I.MX6 does not support cache coherency (in hardware). Therefore it may

be recommended to configure shared memory area as non-cached, if several

bus masters can access it.

Have a great day,
Yuri

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Re: Linux and Bare Metal with shared memory and cache coherency settings?

christoph8446 — Fri, 01 Dec 2017 10:21:54 GMT

Hello,

The SCU maintain data cache coherency between the Cortex-A9 processors right.

Regards

Chris

Re: Linux and Bare Metal with shared memory and cache coherency settings?

jonathanankers — Mon, 26 Feb 2018 08:04:42 GMT

Hello Yuri,

I am having a similar problem - but I don't understand your answer. I thought L1 cache coherency is part of the ARM A9 MPCore architecture? It should be managed through the use of the SMP bit in the ACTLR and the SCU?

Are you saying that I cannot use the SMP bit and the SCU (along with configuring a memory region as shared in the MMU map) to create cache coherent memory areas between A9 cores?

Regards,

Jon

Re: Linux and Bare Metal with shared memory and cache coherency settings?

Yuri — Tue, 27 Feb 2018 06:12:50 GMT

Hello,

You may look at erratum ERR004325 [ARM/MP: 764369—Data or unified cache line maintenance

operation by MVA may not succeed on an Inner Shareable memory region] and try its workaround.

https://www.nxp.com/docs/en/errata/IMX6DQCE.pdf

Regards,

Yuri.