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    <title>i.MX ProcessorsのトピックRe: Bare Metal interface access on MX7</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Bare-Metal-interface-access-on-MX7/m-p/751051#M116887</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Lars&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;for baremetal examples one can look on FreeRTOS&lt;/P&gt;&lt;P&gt;Board Support Packages (3)&lt;BR /&gt;FreeRTOS_iMX7D_1.0.1&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="https://www.nxp.com/products/processors-and-microcontrollers/applications-processors/i.mx-applications-processors/i.mx-7-processors/i.mx-7dual-processors-heterogeneous-processing-with-dual-arm-cortex-a7-cores-and-cortex-m4-core:i.MX7D?tab=Design_Tools_Tab" title="https://www.nxp.com/products/processors-and-microcontrollers/applications-processors/i.mx-applications-processors/i.mx-7-processors/i.mx-7dual-processors-heterogeneous-processing-with-dual-arm-cortex-a7-cores-and-cortex-m4-core:i.MX7D?tab=Design_Tools_Tab"&gt;i.MX 7Dual Arm Cortex-A7 Processor|NXP&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;gt;Is the M4 capable of accessing the DDR RAM or is this RAM access&lt;/P&gt;&lt;P&gt;&amp;gt;exclusive for the A7? Again, any example code?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;yes, examples can be found in FreeRTOS&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 28 Dec 2017 23:17:47 GMT</pubDate>
    <dc:creator>igorpadykov</dc:creator>
    <dc:date>2017-12-28T23:17:47Z</dc:date>
    <item>
      <title>Bare Metal interface access on MX7</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Bare-Metal-interface-access-on-MX7/m-p/751050#M116886</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello community,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;to verify custom hardware I'd like to read/write some bytes to/from different interfaces/memory.&lt;/P&gt;&lt;P&gt;Beacuse I dont know anything about Linux (and the linux part for this project will be done by someone else) I would like to program these tests bare metal.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;KEIL is available, what kind of emulators may I use? Any?&lt;/P&gt;&lt;P&gt;Are there any examples for bare metal&amp;nbsp;interface access?&lt;/P&gt;&lt;P&gt;Is the M4 capable of accessing the DDR RAM or is this RAM access exclusive for the A7? Again, any example code?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks and regards,&lt;BR /&gt;Lars&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 28 Dec 2017 15:54:33 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Bare-Metal-interface-access-on-MX7/m-p/751050#M116886</guid>
      <dc:creator>demoniacmilk</dc:creator>
      <dc:date>2017-12-28T15:54:33Z</dc:date>
    </item>
    <item>
      <title>Re: Bare Metal interface access on MX7</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Bare-Metal-interface-access-on-MX7/m-p/751051#M116887</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Lars&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;for baremetal examples one can look on FreeRTOS&lt;/P&gt;&lt;P&gt;Board Support Packages (3)&lt;BR /&gt;FreeRTOS_iMX7D_1.0.1&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="https://www.nxp.com/products/processors-and-microcontrollers/applications-processors/i.mx-applications-processors/i.mx-7-processors/i.mx-7dual-processors-heterogeneous-processing-with-dual-arm-cortex-a7-cores-and-cortex-m4-core:i.MX7D?tab=Design_Tools_Tab" title="https://www.nxp.com/products/processors-and-microcontrollers/applications-processors/i.mx-applications-processors/i.mx-7-processors/i.mx-7dual-processors-heterogeneous-processing-with-dual-arm-cortex-a7-cores-and-cortex-m4-core:i.MX7D?tab=Design_Tools_Tab"&gt;i.MX 7Dual Arm Cortex-A7 Processor|NXP&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;gt;Is the M4 capable of accessing the DDR RAM or is this RAM access&lt;/P&gt;&lt;P&gt;&amp;gt;exclusive for the A7? Again, any example code?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;yes, examples can be found in FreeRTOS&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 28 Dec 2017 23:17:47 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Bare-Metal-interface-access-on-MX7/m-p/751051#M116887</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2017-12-28T23:17:47Z</dc:date>
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