topic Using ENET1_REF_CLK_25M on IMX6UL in i.MX Processors

Using ENET1_REF_CLK_25M on IMX6UL

andrewparlane2 — Thu, 15 Feb 2018 18:24:43 GMT

We have a custom board with a IMX6UL. The IMX is connected to a generic PHY using RMII.

ENET1_TX_CLK is configured as ENET1_REF_CLK1, and should be an output from the PHY at 25MHz (I think).

ENET2_RX_EN is configured as ENET1_REF_CLK_25M and should be an output from the IMX to the PHY at 25MHz.

I'm using u-boot ATM, and have the following code:

static iomux_v3_cfg_t const fec1_pads[] = {
   ...
   MX6_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
   MX6_PAD_ENET2_RX_EN__ENET1_REF_CLK_25M | MUX_PAD_CTRL(ENET_CLK_PAD_CTRL),
   ...
};
int board_eth_init(bd_t *bis)
{
   imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads));
   ...
}
static int setup_fec(void)
{
struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
int ret;
// Use ENET1_TX_CLK as an input
// Set GRP1[13] - ENET1_CLK_SEL - get ENET1 Tx clk from ENET1_TX_CLK pin
// clear GPR1[17] - ENET1_TX_CLK_DIR - output driver is disabled
clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC1_MASK,
IOMUX_GPR1_FEC1_CLOCK_MUX2_SEL_MASK);
ret = enable_fec_anatop_clock(0, ENET_25MHZ);
if (ret)
{
printf("Failed to enable clock\n");
return ret;
}
enable_enet_clk(1);
return 0;
}

Unfortunately there appears to be nothing outputted on the REF_CLK_25M signal.

I can't see much in the TRM on how to enable this. As far as I can tell just muxing the ENET2_RX_EN as ENET1_REF_CLK_25M should be enough. There's no reference to clock gating or anything else that I can find.

Any ideas?

Thanks,

Andrew

Re: Using ENET1_REF_CLK_25M on IMX6UL

igorpadykov — Thu, 15 Feb 2018 23:05:38 GMT

Hi Andrew

for muxing ENET2_RX_EN as ENET1_REF_CLK_25M one can use

sect.30.5.55 SW_MUX_CTL_PAD_ENET2_RX_EN SW MUX Control
Register (IOMUXC_SW_MUX_CTL_PAD_ENET2_RX_EN) i.MX6UL Reference Manual

http://www.nxp.com/docs/en/reference-manual/IMX6ULRM.pdf

Best regards
igor
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Re: Using ENET1_REF_CLK_25M on IMX6UL

andrewparlane2 — Thu, 15 Feb 2018 23:32:56 GMT

Hi Igor,

I had the muxing set OK.

The problem was the BM_ANADIG_PLL_ENET_REF_25M_ENABLE bit in the pll_enet register.

Andrew