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    <title>topic Order of DDR calibration function call in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Order-of-DDR-calibration-function-call/m-p/748156#M116325</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;In&amp;nbsp;mx6sabresd.c function &lt;EM&gt;board_init_f,&lt;/EM&gt; would it be okay to move function call &lt;EM&gt;spl_dram_init&lt;/EM&gt; to be done after&amp;nbsp;&lt;/P&gt;&lt;P&gt;board_early_init_f?&lt;/P&gt;&lt;P&gt;Since after that function I2C is setup and I get info about the board version to know which DCD table (for DDR calibration) that should be used?&lt;/P&gt;&lt;P&gt;I noticed if I do another&amp;nbsp;&lt;EM&gt;spl_dram_init&lt;/EM&gt;&lt;SPAN&gt;&lt;SPAN&gt;&amp;nbsp;(if I keep the first one) to be called after&amp;nbsp;board_early_init_f, the CPU will not boot up.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Niklas&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 04 Jun 2018 03:16:13 GMT</pubDate>
    <dc:creator>niklasmolin</dc:creator>
    <dc:date>2018-06-04T03:16:13Z</dc:date>
    <item>
      <title>Order of DDR calibration function call</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Order-of-DDR-calibration-function-call/m-p/748156#M116325</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;In&amp;nbsp;mx6sabresd.c function &lt;EM&gt;board_init_f,&lt;/EM&gt; would it be okay to move function call &lt;EM&gt;spl_dram_init&lt;/EM&gt; to be done after&amp;nbsp;&lt;/P&gt;&lt;P&gt;board_early_init_f?&lt;/P&gt;&lt;P&gt;Since after that function I2C is setup and I get info about the board version to know which DCD table (for DDR calibration) that should be used?&lt;/P&gt;&lt;P&gt;I noticed if I do another&amp;nbsp;&lt;EM&gt;spl_dram_init&lt;/EM&gt;&lt;SPAN&gt;&lt;SPAN&gt;&amp;nbsp;(if I keep the first one) to be called after&amp;nbsp;board_early_init_f, the CPU will not boot up.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks,&lt;/P&gt;&lt;P&gt;Niklas&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 04 Jun 2018 03:16:13 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Order-of-DDR-calibration-function-call/m-p/748156#M116325</guid>
      <dc:creator>niklasmolin</dc:creator>
      <dc:date>2018-06-04T03:16:13Z</dc:date>
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    <item>
      <title>Re: Order of DDR calibration function call</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Order-of-DDR-calibration-function-call/m-p/748157#M116326</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Niklas&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;usually ddr initialization is performed as first step, then other peripherals&lt;/P&gt;&lt;P&gt;are initialized. More proper way to post it on uboot mail list as nxp does not use&lt;/P&gt;&lt;P&gt;spl in its i.MX6 uboot releases.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 04 Jun 2018 07:54:20 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Order-of-DDR-calibration-function-call/m-p/748157#M116326</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2018-06-04T07:54:20Z</dc:date>
    </item>
    <item>
      <title>Re: Order of DDR calibration function call</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Order-of-DDR-calibration-function-call/m-p/748158#M116327</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Igor.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks for your response.&lt;/P&gt;&lt;P&gt;The question I have is if there could be an issue if I do the DDR calibration after the peripheral clocks etc. are enabled?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Niklas&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 04 Jun 2018 16:40:19 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Order-of-DDR-calibration-function-call/m-p/748158#M116327</guid>
      <dc:creator>niklasmolin</dc:creator>
      <dc:date>2018-06-04T16:40:19Z</dc:date>
    </item>
    <item>
      <title>Re: Order of DDR calibration function call</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Order-of-DDR-calibration-function-call/m-p/748159#M116328</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV class=""&gt;&lt;P&gt;Hi Niklas&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;yes there may be potential issues as enabling peripheral clocks&amp;nbsp;&lt;/P&gt;may affect mmdc parent frequency and introduce additional noise&lt;/DIV&gt;&lt;DIV class=""&gt;on board.&lt;BR /&gt;&amp;nbsp;&lt;P&gt;Regards,&lt;/P&gt;&lt;P&gt;Niklas&lt;/P&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 04 Jun 2018 23:41:08 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Order-of-DDR-calibration-function-call/m-p/748159#M116328</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2018-06-04T23:41:08Z</dc:date>
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