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    <title>i.MX Processors中的主题 IMX7D to LPDDR3 interface clock termination</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/IMX7D-to-LPDDR3-interface-clock-termination/m-p/746339#M116115</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We are using &lt;SPAN class=""&gt;MCIMX7D3EVK10SD in our design with&amp;nbsp;&lt;SPAN&gt;08EMCP08-EL3DT227-A01U&amp;nbsp;(Kingston Memory) using LPDDR3 interface.&lt;/SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Kindly suggest what type termination need to be provided for DDR_Clock in&amp;nbsp; LPDDR3 interface. I could not find any recommendation for DDR_Clock Termination and in WARP board design no termination was used. Kindly suggest suitable termination or shall we connect as such in WARP schematics design.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks &amp;amp; Regards,&lt;/P&gt;&lt;P&gt;Logesh&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Tue, 26 Dec 2017 14:54:59 GMT</pubDate>
    <dc:creator>logeshs</dc:creator>
    <dc:date>2017-12-26T14:54:59Z</dc:date>
    <item>
      <title>IMX7D to LPDDR3 interface clock termination</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX7D-to-LPDDR3-interface-clock-termination/m-p/746339#M116115</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We are using &lt;SPAN class=""&gt;MCIMX7D3EVK10SD in our design with&amp;nbsp;&lt;SPAN&gt;08EMCP08-EL3DT227-A01U&amp;nbsp;(Kingston Memory) using LPDDR3 interface.&lt;/SPAN&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Kindly suggest what type termination need to be provided for DDR_Clock in&amp;nbsp; LPDDR3 interface. I could not find any recommendation for DDR_Clock Termination and in WARP board design no termination was used. Kindly suggest suitable termination or shall we connect as such in WARP schematics design.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks &amp;amp; Regards,&lt;/P&gt;&lt;P&gt;Logesh&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 26 Dec 2017 14:54:59 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX7D-to-LPDDR3-interface-clock-termination/m-p/746339#M116115</guid>
      <dc:creator>logeshs</dc:creator>
      <dc:date>2017-12-26T14:54:59Z</dc:date>
    </item>
    <item>
      <title>Re: IMX7D to LPDDR3 interface clock termination</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IMX7D-to-LPDDR3-interface-clock-termination/m-p/746340#M116116</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Logesh&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;please refer to sect.3. i.MX7 series layout recommendations Hardware Development&lt;/P&gt;&lt;P&gt;Guide for i.MX7Dual and 7Solo Applications Processors, termination is not used.&lt;BR /&gt;&lt;A class="jive-link-external-small" href="https://community.nxp.com/external-link.jspa?url=http%3A%2F%2Fwww.nxp.com%2Ffiles%2F32bit%2Fdoc%2Fuser_guide%2FIMX7DSHDG.pdf" rel="nofollow" target="_blank"&gt;http://www.nxp.com/files/32bit/doc/user_guide/IMX7DSHDG.pdf&lt;/A&gt;&lt;/P&gt;&lt;P&gt;In general recommended to perform signal integrity (SI) simulations.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 26 Dec 2017 23:02:32 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IMX7D-to-LPDDR3-interface-clock-termination/m-p/746340#M116116</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2017-12-26T23:02:32Z</dc:date>
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