topic Re: IMX6 PCIe RC BAR in i.MX Processors

IMX6 PCIe RC BAR

amnatehreem — Wed, 14 Feb 2018 12:42:49 GMT

Hi,

I am trying to read RC BAR0 register of PCI express in imx6.

According to the manual:

In case of memory BAR, the last 4 bits are read-only and give the BAR type.
In case of I/O BAR, last 2 bits are read-only. Last bit shows the BAR type, second last bit is 0 and bit 2 is the least significant bit of base address.

Before writing 0xFFFFFFFF to the BAR0 register, it reads as 0x0000000C and after writing 0xFFFFFFFF to it, it reads as 0xFFF0000F which is confusing for me because according to my understanding, the last bits shouldn't be writable.

In the Linux driver, I have seen that BAR0 is being set before the link up with the value 0x00000004. I have tried it but again I get the same value(0xFFF0000F ) when I read it back after writing it with 0xFFFFFFFF.

The manual also says that the BAR registers are configurable that the BAR mask register determines the number of writable bits in the BAR. I have searched the manual, there are BAR mask registers for EP mode but there isn't any such register for RC mode.

Any help would be truely appreciated.

Regards,

Amna

Re: IMX6 PCIe RC BAR

Yuri — Thu, 15 Feb 2018 07:38:10 GMT

Hello,

Please verify if PCIe module is clocked.

Also, hope, the following helps.

IMX6 PCIe EP Cannot configure BAR1

Have a great day,

Yuri

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Re: IMX6 PCIe RC BAR

amnatehreem — Thu, 15 Feb 2018 08:30:21 GMT

Hi Yuri,

Thank you for replying. I have looked into the link you have attached, there aren't any mask registers in RC mode so I cannot use them. And also PCI is properly clocked. At this stage, I am reading and writing to endpoint configuration space as well.

BAR registers are configurable in IMX6 so the last 4 bits are writable. But after configuring the BARs, there should be a mechanism (like BAR mask registers in EP mode) to make them read-only so that they don't change when written afterward. I cannot find how to do that.

Regards,

Amna