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    <title>i.MX ProcessorsのトピックRe: EIM timing definition</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/EIM-timing-definition/m-p/744036#M115800</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi igor,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I might not have understood that your first answer correctly.&lt;/P&gt;&lt;P&gt;You told me that "timings are the same" at your first answer on this thread.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I am worried about typo for EIM timing which described on datasheet.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Kazuma Sasaki.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Wed, 27 Dec 2017 01:02:06 GMT</pubDate>
    <dc:creator>Kazuma_Sasaki</dc:creator>
    <dc:date>2017-12-27T01:02:06Z</dc:date>
    <item>
      <title>EIM timing definition</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/EIM-timing-definition/m-p/744032#M115796</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Community, &lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;We are developing custom board with i.MX6D. However, we can not clearly understand specification of EIM timing parameters.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;From IMX6DQAEC REV.5&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_6.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/34521i20930FA53DE11C18/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_6.png" alt="pastedImage_6.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_7.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/34492i0CDFEB9244F12634/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_7.png" alt="pastedImage_7.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Linux BSP implementation:&lt;/P&gt;&lt;P&gt;&amp;nbsp; AXI_CLK_ROOT = 198MHz = PLL2 PFD2 396MHz / 2&lt;/P&gt;&lt;P&gt;&amp;nbsp; ACLK_EIM_SLOW_CLK_ROOT = 99MHz = AXI_CLK_ROOT / 2&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Questions:&lt;/P&gt;&lt;P&gt;Q1.&lt;/P&gt;&lt;P&gt;The datasheet is described that "t means clock period from axi_clk frequency".&lt;/P&gt;&lt;P&gt;In above case, should we use AXI_CLK_ROOT(198MHz) for "clock period for t"?&lt;/P&gt;&lt;P&gt;I suppose we should use ACLK_EIM_SLOW_CLK_ROOT(99MHz) instead of AXI_CLK_ROOT(198MHz). Is it right?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Q2.&lt;/P&gt;&lt;P&gt;From IMX6SDLAEC REV.8&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_8.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/34574iE492A844B21C1382/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_8.png" alt="pastedImage_8.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;EIM timing definitions are different between i.MX6S/DL and i.MX6D/Q/DP/QP such as above figures.&lt;/P&gt;&lt;P&gt;I suppose i.MX6S and i.MX6D are using same EIM controller. but, why timing definitions are different as above?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Kazuma Sasaki.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 25 Dec 2017 08:40:04 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/EIM-timing-definition/m-p/744032#M115796</guid>
      <dc:creator>Kazuma_Sasaki</dc:creator>
      <dc:date>2017-12-25T08:40:04Z</dc:date>
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    <item>
      <title>Re: EIM timing definition</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/EIM-timing-definition/m-p/744033#M115797</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Kazuma&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;1.&amp;gt; I suppose we should use ACLK_EIM_SLOW_CLK_ROOT(99MHz) instead of AXI_CLK_ROOT(198MHz). Is it right?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;right&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;2. &amp;gt;why timing definitions are different as above?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;timings are the same, first makes more sense as according to&lt;/P&gt;&lt;P&gt;EIM EIM_CSnRCR1 definition CSA is EIM clock cycles, so "unit" is given&lt;/P&gt;&lt;P&gt;as combination "t"&amp;amp;CSA.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 25 Dec 2017 23:01:01 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/EIM-timing-definition/m-p/744033#M115797</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2017-12-25T23:01:01Z</dc:date>
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    <item>
      <title>Re: EIM timing definition</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/EIM-timing-definition/m-p/744034#M115798</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi igor,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I appreciate your support. Let me confirm regarding Q2.&lt;/P&gt;&lt;P&gt;&amp;lt;Conditions&amp;gt;&lt;/P&gt;&lt;P&gt;(1) CSA = 1 cycle&lt;/P&gt;&lt;P&gt;(2) ACLK_EIM_SLOW_CLK_ROOT = 99MHz = 10.1 ns time per cycle&lt;/P&gt;&lt;P&gt;(3) Timing definition&lt;/P&gt;&lt;P&gt;From IMX6DQAEC REV.5&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_6.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/34523i827A77A18EBB678C/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_6.png" alt="pastedImage_6.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_7.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/34577i7556B8370A69B654/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_7.png" alt="pastedImage_7.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;From IMX6SDLAEC REV.8&lt;/P&gt;&lt;P&gt;&lt;span class="lia-inline-image-display-wrapper" image-alt="pastedImage_8.png"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/34611iF10012B1D21D45E2/image-size/large?v=v2&amp;amp;px=999" role="button" title="pastedImage_8.png" alt="pastedImage_8.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;P&gt;&amp;lt;Calculation&amp;gt;&lt;/P&gt;&lt;P&gt;In case of i.MX6D : WE31 MAX = 3.5 - CSA x t = 3.5 - 10.1 = -6.6ns&lt;/P&gt;&lt;P&gt;In case of i.MX6S : WE31 MAX = 3 - CSA = 3 - 10.1 = -7.1ns&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&amp;lt;Question&amp;gt;&lt;/P&gt;&lt;P&gt;Is the above calculation correct? If correct, why timings are same in above case?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Kazuma Sasaki.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 26 Dec 2017 09:17:44 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/EIM-timing-definition/m-p/744034#M115798</guid>
      <dc:creator>Kazuma_Sasaki</dc:creator>
      <dc:date>2017-12-26T09:17:44Z</dc:date>
    </item>
    <item>
      <title>Re: EIM timing definition</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/EIM-timing-definition/m-p/744035#M115799</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Kazuma&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I think calculations are correct.&lt;/P&gt;&lt;P&gt;Where did you see that timings are same ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 26 Dec 2017 11:01:18 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/EIM-timing-definition/m-p/744035#M115799</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2017-12-26T11:01:18Z</dc:date>
    </item>
    <item>
      <title>Re: EIM timing definition</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/EIM-timing-definition/m-p/744036#M115800</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi igor,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I might not have understood that your first answer correctly.&lt;/P&gt;&lt;P&gt;You told me that "timings are the same" at your first answer on this thread.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I am worried about typo for EIM timing which described on datasheet.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Kazuma Sasaki.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 27 Dec 2017 01:02:06 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/EIM-timing-definition/m-p/744036#M115800</guid>
      <dc:creator>Kazuma_Sasaki</dc:creator>
      <dc:date>2017-12-27T01:02:06Z</dc:date>
    </item>
    <item>
      <title>Re: EIM timing definition</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/EIM-timing-definition/m-p/744037#M115801</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;DIV class=""&gt;&lt;P&gt;Hi Kazuma&amp;nbsp;&lt;/P&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;if you mean WE31, they are not the same.&lt;BR /&gt;&lt;P style="min-height: 8pt; padding: 0px;"&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;/P&gt;&lt;/DIV&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 27 Dec 2017 05:04:25 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/EIM-timing-definition/m-p/744037#M115801</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2017-12-27T05:04:25Z</dc:date>
    </item>
    <item>
      <title>Re: EIM timing definition</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/EIM-timing-definition/m-p/744038#M115802</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Igor,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I got it. thank you so much for your support.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best Regards,&lt;/P&gt;&lt;P&gt;Kazuma Sasaki.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Wed, 27 Dec 2017 08:44:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/EIM-timing-definition/m-p/744038#M115802</guid>
      <dc:creator>Kazuma_Sasaki</dc:creator>
      <dc:date>2017-12-27T08:44:42Z</dc:date>
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