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    <title>i.MX Processors中的主题 Re: Three wire SPI Interface Test</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/Three-wire-SPI-Interface-Test/m-p/743293#M115646</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Anshul&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;board uses ECSPI4_SCLK,ECSPI4_SS0,ECSPI4_MOSI,ECSPI4_MISO, if&lt;/P&gt;&lt;P&gt;some of these signals are not used by external SPI device, they may be ignored&lt;/P&gt;&lt;P&gt;without additional configuration. For example according to sect.20.4.1 Master Mode i.MX6UL Reference Manual:&lt;BR /&gt;One of the Chip Select (SS) signals and the clock signal (SCLK) are used to transfer data&lt;BR /&gt;between two devices. If the external device is a transmit-only device, the ECSPI master's&lt;BR /&gt;output port can be ignored and used for other purposes.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Mon, 22 Jan 2018 11:27:07 GMT</pubDate>
    <dc:creator>igorpadykov</dc:creator>
    <dc:date>2018-01-22T11:27:07Z</dc:date>
    <item>
      <title>Three wire SPI Interface Test</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Three-wire-SPI-Interface-Test/m-p/743292#M115645</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello All,&lt;/P&gt;&lt;P&gt;i am using imx6ul board, and in that i am enabling SPI Driver but it is a 4 wire interface ,&lt;/P&gt;&lt;P&gt;as per the requirement i need to&amp;nbsp;test 3 wire interface test SPI.&lt;/P&gt;&lt;P&gt;is there any possibility that i can perform this test.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;--Anshul&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 22 Jan 2018 10:48:31 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Three-wire-SPI-Interface-Test/m-p/743292#M115645</guid>
      <dc:creator>anshulkhare</dc:creator>
      <dc:date>2018-01-22T10:48:31Z</dc:date>
    </item>
    <item>
      <title>Re: Three wire SPI Interface Test</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/Three-wire-SPI-Interface-Test/m-p/743293#M115646</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Anshul&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;board uses ECSPI4_SCLK,ECSPI4_SS0,ECSPI4_MOSI,ECSPI4_MISO, if&lt;/P&gt;&lt;P&gt;some of these signals are not used by external SPI device, they may be ignored&lt;/P&gt;&lt;P&gt;without additional configuration. For example according to sect.20.4.1 Master Mode i.MX6UL Reference Manual:&lt;BR /&gt;One of the Chip Select (SS) signals and the clock signal (SCLK) are used to transfer data&lt;BR /&gt;between two devices. If the external device is a transmit-only device, the ECSPI master's&lt;BR /&gt;output port can be ignored and used for other purposes.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 22 Jan 2018 11:27:07 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/Three-wire-SPI-Interface-Test/m-p/743293#M115646</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2018-01-22T11:27:07Z</dc:date>
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