i.MX ProcessorsのトピックRe: i.mx6ULL USB Hardware Clarification and USB Detection.

i.mx6ULL USB Hardware Clarification and USB Detection.

theevanvenugopa — Tue, 13 Feb 2018 07:35:10 GMT

Hi NXP team,

Am very sad to inform you that I didn't get a response to previous emails.

Expecting your support for the following query.

1. In our custom board based on i.mx6ULL, we are only using the board only in USB device mode. For this, the Vbus(in our case it is USB_VBUS_iMX) voltage is necessary to connect to the i.MX's T12 pin??????(from HDG document I came to know that VBUS has no part in Power up sequence)

2. In the NXP EVK, we found a circuit as below. May I know the necessity of the same(Related to concern No:1)?

3. USB Data transfer detection is possible in i.MX? If yes, please provide the necessary details for implementing the same.

Re: i.mx6ULL USB Hardware Clarification and USB Detection.

Yuri — Fri, 16 Feb 2018 05:20:28 GMT

Hello,

please look at my comments below.

Any of USB_OTG1_VBUS or USB_OTG2_VBUS may be applied for the USB

module of i.MX 6ULL. Your scheme (for USB_OTG1) is correct.

Basically VBUS may be provided directly from the connector.

I have some doubt if USB Data transfer detection is possible without data line

analyzing.

Have a great day,
Yuri

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Re: i.mx6ULL USB Hardware Clarification and USB Detection.

theevanvenugopa — Fri, 16 Feb 2018 05:50:40 GMT

YuriMuhin_ng‌ Thank you for the support.

At power-up sequence time, is that okay if VBUS reaches i.mx before DCDC_3V3? Also in the absence of DCDC_3V3(Power switch is OFF), Whether the presence of VBUS harms the IC?

Re: i.mx6ULL USB Hardware Clarification and USB Detection.

Yuri — Mon, 19 Feb 2018 03:16:31 GMT

Hello,

This already has been discussed.

https://community.nxp.com/message/966176

Regards,

Yuri.