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    <title>topic imx6Q，BCLK not work in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/imx6Q-BCLK-not-work/m-p/740392#M115231</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;TABLE&gt;&lt;TBODY&gt;&lt;TR&gt;&lt;TD width="550"&gt;&lt;SPAN class=""&gt;1 The burst clock runs whenever ACLK is active (independent of chip select configuration)&lt;/SPAN&gt;&lt;/TD&gt;&lt;/TR&gt;&lt;/TBODY&gt;&lt;/TABLE&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;I tried activating the BCLK continuously on my i.MX6Q board by setting ('1') the BCM bit (bit 0) on the EIM_WCR (0x021B_8090h) register.&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;I am not getting any clock on BLCK - constant '0'.&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;Did I forget anything?&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;here is my register configuration&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK, &amp;nbsp;//pin_conf&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;writel(0x00020081, ram_reg);&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;//EIM_CS0GCR1&amp;nbsp;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;writel(0x00000001, ram_reg + 0x90); &amp;nbsp;// &lt;SPAN class=""&gt;EIM_WCR&lt;/SPAN&gt; &lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;someone help me ,what should i do to solve this problem??&lt;span class="lia-inline-image-display-wrapper"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/19904i78D1F982C126BA9D/image-size/large?v=v2&amp;amp;px=999" title="pastedImage_1.png" alt="pastedImage_1.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Sat, 20 Jan 2018 01:42:03 GMT</pubDate>
    <dc:creator>liupeiliu</dc:creator>
    <dc:date>2018-01-20T01:42:03Z</dc:date>
    <item>
      <title>imx6Q，BCLK not work</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx6Q-BCLK-not-work/m-p/740392#M115231</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;TABLE&gt;&lt;TBODY&gt;&lt;TR&gt;&lt;TD width="550"&gt;&lt;SPAN class=""&gt;1 The burst clock runs whenever ACLK is active (independent of chip select configuration)&lt;/SPAN&gt;&lt;/TD&gt;&lt;/TR&gt;&lt;/TBODY&gt;&lt;/TABLE&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;I tried activating the BCLK continuously on my i.MX6Q board by setting ('1') the BCM bit (bit 0) on the EIM_WCR (0x021B_8090h) register.&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;I am not getting any clock on BLCK - constant '0'.&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;Did I forget anything?&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;here is my register configuration&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;MX6Q_PAD_EIM_BCLK__WEIM_WEIM_BCLK, &amp;nbsp;//pin_conf&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;writel(0x00020081, ram_reg);&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;&amp;nbsp;//EIM_CS0GCR1&amp;nbsp;&lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;writel(0x00000001, ram_reg + 0x90); &amp;nbsp;// &lt;SPAN class=""&gt;EIM_WCR&lt;/SPAN&gt; &lt;/P&gt;&lt;P style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;someone help me ,what should i do to solve this problem??&lt;span class="lia-inline-image-display-wrapper"&gt;&lt;img src="https://community.nxp.com/t5/image/serverpage/image-id/19904i78D1F982C126BA9D/image-size/large?v=v2&amp;amp;px=999" title="pastedImage_1.png" alt="pastedImage_1.png" /&gt;&lt;/span&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sat, 20 Jan 2018 01:42:03 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx6Q-BCLK-not-work/m-p/740392#M115231</guid>
      <dc:creator>liupeiliu</dc:creator>
      <dc:date>2018-01-20T01:42:03Z</dc:date>
    </item>
    <item>
      <title>Re: imx6Q，BCLK not work</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx6Q-BCLK-not-work/m-p/740393#M115232</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Hello,&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; &lt;BR /&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;1.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; What is content of the following registers?&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;1.1.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK Pad Mux Register&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;at address: 0x020E_0158&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;1.2.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK Pad Control Register&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;at address: 0x020E_046C&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;2.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; According section 22.5.4 [Burst Clock Divisor (BCD)] of i.MX 6Dual/6Quad Applications Processor Reference Manual, Rev. 4, 09/2017:&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;“The BCM bit is used mainly for system debug mode. It has no functional use of the EIM in normal mode.” Note, the i.MX6 D/Q does not have special PLL for providing continuous BCLK, synchronized with internal (system bus) ACLK. This feature is supported in i.MX6 S/DL. So, for i.MX6 DQ we cannotguarantee, that BCLK in continuous mode is fully synchronized with ACLK. &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&amp;nbsp;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Have a great day,&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Yuri&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;------------------------------------------------------------------------------&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Note: If this post answers your question, please click the Correct &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Answer button. Thank you!&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 23 Jan 2018 07:35:11 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx6Q-BCLK-not-work/m-p/740393#M115232</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2018-01-23T07:35:11Z</dc:date>
    </item>
    <item>
      <title>Re: imx6Q，BCLK not work</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/imx6Q-BCLK-not-work/m-p/740394#M115233</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;hello&amp;nbsp;&lt;/P&gt;&lt;P class="" style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;SPAN class="" style="border: 0px; font-weight: inherit;"&gt;&amp;nbsp; IOMUXC_SW_MUX_CTL_PAD_EIM_BCLK Pad Mux Register&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="" style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;SPAN class="" style="border: 0px; font-weight: inherit;"&gt;at address: 0x020E_0158&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="" style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;SPAN class="" style="border: 0px; font-weight: inherit;"&gt;&amp;nbsp; IOMUXC_SW_PAD_CTL_PAD_EIM_BCLK Pad Control Register&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="" style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;SPAN class="" style="border: 0px; font-weight: inherit;"&gt;at address: 0x020E_046C&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="" style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;SPAN class="" style="border: 0px; font-weight: inherit;"&gt;these two Register value is reset value ,i&amp;nbsp;&lt;SPAN style="color: #2e3033; background-color: #eef0f2; font-size: 12px;"&gt;&amp;nbsp;printed out the contents of the register,MUX_CTL_PAD(0158h) is 0 , PAD_CTL_PAD(046ch) is b0b1.&lt;/SPAN&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="" style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;SPAN style="background-color: #ffffff; border: 0px; color: #51626f; font-weight: inherit; font-size: 15px;"&gt;“The BCM bit is used mainly for system debug mode. It has no functional use of the EIM in normal mode.”&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="" style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;SPAN style="color: #2e3033; background-color: #eef0f2; font-size: 12px;"&gt;How do I set my board debug mode?&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="" style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;SPAN style="background-color: #ffffff; color: #51626f; font-size: 15px;"&gt;This feature is supported in i.MX6 S/DL. So, for i.MX6 DQ we cannotguarantee?&lt;/SPAN&gt;&lt;/P&gt;&lt;P class="" style="color: #51626f; background-color: #ffffff; border: 0px;"&gt;&lt;SPAN style="background-color: #ffffff; color: #51626f; font-size: 15px;"&gt;What does this mean? &amp;nbsp;the i.mx6Q does not supported??&lt;/SPAN&gt;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Tue, 23 Jan 2018 07:53:38 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/imx6Q-BCLK-not-work/m-p/740394#M115233</guid>
      <dc:creator>liupeiliu</dc:creator>
      <dc:date>2018-01-23T07:53:38Z</dc:date>
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