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    <title>i.MX ProcessorsのトピックRe: IPU, CSI Timing</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/IPU-CSI-Timing/m-p/739546#M115067</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thanks Bio_TICFSL,&lt;/P&gt;&lt;P&gt;I have not found where they talk about timing in the first link, while the second one is really a good hint.&lt;/P&gt;&lt;P&gt;I found in the manual that there are special register in the IPU for image timing:&amp;nbsp;SENS_FRM_WIDTH, SENS_FRM_HEIGHT,&amp;nbsp;HSC, VSC, ACT_FRM_HEIGHT and ACT_FRM_WIDTH.&lt;/P&gt;&lt;P&gt;Any good starting points about understating how this registers are integrating in the mxc_capture framework?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Thu, 31 May 2018 16:44:48 GMT</pubDate>
    <dc:creator>ieio</dc:creator>
    <dc:date>2018-05-31T16:44:48Z</dc:date>
    <item>
      <title>IPU, CSI Timing</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IPU-CSI-Timing/m-p/739544#M115065</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi all,&lt;/P&gt;&lt;P&gt;I am working to a camera driver, and I am testing it with gstreamer.&lt;/P&gt;&lt;P&gt;My gst pipe is&amp;nbsp;gst-launch-1.0 -e -v imxv4l2videosrc device=/dev/video0 ! imxipuvideosink so I a using&amp;nbsp;mxc_v4l2_capture.c&lt;/P&gt;&lt;P&gt;If I well understood I set CSIn (primary, secondary) and I link it to a IPU (IPU0 and IPU1) and in the IPU the image can be elaborated (deinterlaced,rotated, converted).&lt;/P&gt;&lt;P&gt;My doubt is: as I have camera timings like, Active Vertical Width, Total Vertical Width, Vertical Back Porch and so on, where I should set this timings in the IPU?&lt;/P&gt;&lt;P&gt;If it is not in the IPU where they should be set where, should I set them?&lt;/P&gt;&lt;P&gt;Please point me to the code that handle input video timings.&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 31 May 2018 12:49:33 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IPU-CSI-Timing/m-p/739544#M115065</guid>
      <dc:creator>ieio</dc:creator>
      <dc:date>2018-05-31T12:49:33Z</dc:date>
    </item>
    <item>
      <title>Re: IPU, CSI Timing</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IPU-CSI-Timing/m-p/739545#M115066</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi ieio,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The following link will help you with timming:&lt;/P&gt;&lt;P&gt;&lt;A _jive_internal="true" class="link-titled" href="https://community.nxp.com/message/579476?commentID=579476#comment-579476" title="https://community.nxp.com/message/579476?commentID=579476#comment-579476"&gt;https://community.nxp.com/message/579476&lt;/A&gt;&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/thread/468957"&gt;AC timing of IPUx_CSI input signals.&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 31 May 2018 15:47:11 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IPU-CSI-Timing/m-p/739545#M115066</guid>
      <dc:creator>Bio_TICFSL</dc:creator>
      <dc:date>2018-05-31T15:47:11Z</dc:date>
    </item>
    <item>
      <title>Re: IPU, CSI Timing</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/IPU-CSI-Timing/m-p/739546#M115067</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Thanks Bio_TICFSL,&lt;/P&gt;&lt;P&gt;I have not found where they talk about timing in the first link, while the second one is really a good hint.&lt;/P&gt;&lt;P&gt;I found in the manual that there are special register in the IPU for image timing:&amp;nbsp;SENS_FRM_WIDTH, SENS_FRM_HEIGHT,&amp;nbsp;HSC, VSC, ACT_FRM_HEIGHT and ACT_FRM_WIDTH.&lt;/P&gt;&lt;P&gt;Any good starting points about understating how this registers are integrating in the mxc_capture framework?&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Thu, 31 May 2018 16:44:48 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/IPU-CSI-Timing/m-p/739546#M115067</guid>
      <dc:creator>ieio</dc:creator>
      <dc:date>2018-05-31T16:44:48Z</dc:date>
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