Clarification on eDMA use with LPSPI watermark

ryanshuttlewort — Thu, 18 Jan 2018 17:43:16 GMT

Hello, I am using IAR with an RT1050 SDK, version 2.3.0 (2017-11-16). I have been working with the scatter gather example and trying to adapt it to a double-buffered reader of LPSPI data. I am looking for clarification on some things I am seeing in the reference manual:

21.1.3
...
Periodic Trigger mode
In this mode, a DMA source may only request a DMA transfer, such as when a
transmit buffer becomes empty or a receive buffer becomes full, periodically.
Configuration of the period is done in the registers of the periodic interrupt timer
(PIT). This mode is available only for channels 0 to 3
21.4.1 DMA channels with periodic triggering capability
Besides the normal routing functionality, the first 4 channels of the DMAMUX provide a
special periodic triggering capability that can be used to provide an automatic mechanism
to transmit bytes, frames, or packets at fixed intervals without the need for processor
intervention.
The trigger is generated by the periodic interrupt timer (PIT); as such, the configuration
of the periodic triggering interval is done via configuration registers in the PIT. See the
section on periodic interrupt timer for more information on this topic.
Note
Because of the dynamic nature of the system (due to DMA
channel priorities, bus arbitration, interrupt service routine
lengths, etc.), the number of clock cycles between a trigger and
the actual DMA transfer cannot be guaranteed.
Chapter 21 Direct Memory Access Multiplexer (DMAMUX)
i.
38.1 Chip-specific LPSPI information
NOTE
The "Output Triggers" section is not applicable for this device.
38.3.5.1 Output Triggers
The LPSPI generates two output triggers that can be connected to other peripherals on the
device. The frame output trigger asserts at the end of each frame (when PCS negates) and
remains asserted until PCS next asserts. The word output trigger asserts at the end of each
received word and remains asserted for one LPSPI_SCK period.

From the statements above and other experimentation, I am getting the impression that LPSPI eDMA transactions can not be triggered or paced from an LPSPI RX FIFO watermark event. Section 21.1.3 seems to suggest that the recommended way of doing this is to periodically trigger a transfer of a given number of bytes.

Is it possible to trigger an RT1050 eDMA transfer from an LPSPI FIFO hitting a given watermark of is the PIT polling process the only way?

Thanks.

Re: Clarification on eDMA use with LPSPI watermark

Yuri — Fri, 19 Jan 2018 07:44:50 GMT

Hello,

According to Chapter 22 [Enhanced Direct Memory Access (eDMA)]

of i.MX RT1050 Processor Reference Manual, Rev. 0, 10/2017,

there are two options to request channel service:

• Software: setting the TCDn_CSR[START].

• Hardware: slave device asserting its eDMA peripheral request signal.

The DMAMUX should be used in Normal mode.

“In this mode, a DMA source is routed directly to the specified DMA channel.

The operation of the DMAMUX in this mode is completely transparent to the

system.”

Have a great day,
Yuri

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Re: Clarification on eDMA use with LPSPI watermark

Yuri — Wed, 24 Jan 2018 06:11:05 GMT

Hello,

Customers can use i.MXRT1050 EVK Extended Feature Example Code and HW guide

Regards,

Yuri.

topic Clarification on eDMA use with LPSPI watermark in i.MX Processors

Clarification on eDMA use with LPSPI watermark

Re: Clarification on eDMA use with LPSPI watermark

Re: Clarification on eDMA use with LPSPI watermark