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    <title>topic PCIe : Phy link never came up in i.MX Processors</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/PCIe-Phy-link-never-came-up/m-p/734573#M114341</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi guys,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I'm currently implementing PCIe support on an iMX6DL based board. I let the stock device tree configuration, and I get this error log at boot :&amp;nbsp;&lt;/P&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;P&gt;1ffc000.pcie supply pcie-bus not found, using dummy regulator&lt;BR /&gt;imx6q-pcie 1ffc000.pcie: phy link never came up&lt;BR /&gt;imx6q-pcie 1ffc000.pcie: failed to initialize host&lt;BR /&gt;imx6q-pcie: probe of 1ffc000.pcie failed with error -22&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;Does it mean that the iMX PCIe core isn't detected ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I can't get rid of this error, and I can't find any working fix on the internet :-(&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Have a nice day !&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;PinkPR&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 24 Nov 2017 09:44:15 GMT</pubDate>
    <dc:creator>pinkpr</dc:creator>
    <dc:date>2017-11-24T09:44:15Z</dc:date>
    <item>
      <title>PCIe : Phy link never came up</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/PCIe-Phy-link-never-came-up/m-p/734573#M114341</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi guys,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I'm currently implementing PCIe support on an iMX6DL based board. I let the stock device tree configuration, and I get this error log at boot :&amp;nbsp;&lt;/P&gt;&lt;BLOCKQUOTE class="jive_macro_quote jive-quote jive_text_macro"&gt;&lt;P&gt;1ffc000.pcie supply pcie-bus not found, using dummy regulator&lt;BR /&gt;imx6q-pcie 1ffc000.pcie: phy link never came up&lt;BR /&gt;imx6q-pcie 1ffc000.pcie: failed to initialize host&lt;BR /&gt;imx6q-pcie: probe of 1ffc000.pcie failed with error -22&lt;/P&gt;&lt;/BLOCKQUOTE&gt;&lt;P&gt;Does it mean that the iMX PCIe core isn't detected ?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I can't get rid of this error, and I can't find any working fix on the internet :-(&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Have a nice day !&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;PinkPR&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 24 Nov 2017 09:44:15 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/PCIe-Phy-link-never-came-up/m-p/734573#M114341</guid>
      <dc:creator>pinkpr</dc:creator>
      <dc:date>2017-11-24T09:44:15Z</dc:date>
    </item>
    <item>
      <title>Re: PCIe : Phy link never came up</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/PCIe-Phy-link-never-came-up/m-p/734574#M114342</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hello,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; Please look at my comments below.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;1.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; Check PCie clock configuration, if it meets HW Design Checking List recommendations about using (external) PCIe &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;clock :&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;"Due to CLKx_P/N is LVDS port and don't match with PCIe reference clock specification. For PCIe Gen1 application, following low cost solution can be used(DC bias and AC impedance should be considered). Please refer to "HW Design Checking List for i.Mx6DQSDL Rev3.1.xlsx", sheet "Schematic", Ref12 for more info."&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; "PCIe reference clock solution which provided by CLKx_N/P of i.MX6 chip can't pass PCIe Gen2 compliance test. Recommend using external PCIe 2.0/3.0 clock generator with 2 HCSL outputs solution. One clock channel connect to i.MX6 as a reference input, please click Ref14 ("HW Design Checking List for i.Mx6DQSDL Rev3.1.xlsx") for reference circuit. Another clock channel should connect to PCIe connector, please contact generator vendor for detailed design guide."&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&lt;A href="https://community.nxp.com/docs/DOC-93819"&gt;HW_Design_Checking_List_for_i.MX6DQP6DQ6SDL&lt;/A&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;The PCIe clock signal pair is not part of the PCIe PHY IP (assuming the CLK1N/P are used).&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;They are configured via PMU_MISC1n register. &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;2.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; Use the recent NXP BXP.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;A class="link-titled" href="https://www.nxp.com/webapp/Download?colCode=L4.9.11_1.0.0_LINUX_DOCS" title="https://www.nxp.com/webapp/Download?colCode=L4.9.11_1.0.0_LINUX_DOCS"&gt;https://www.nxp.com/webapp/Download?colCode=L4.9.11_1.0.0_LINUX_DOCS&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;Summary page:&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&lt;A class="link-titled" href="https://www.nxp.com/support/developer-resources/run-time-software/i.mx-developer-resources/i.mx-software:IMX_SW" title="https://www.nxp.com/support/developer-resources/run-time-software/i.mx-developer-resources/i.mx-software:IMX_SW"&gt;i.MX 6 / i.MX 7 Series Software and Development Tool|NXP&lt;/A&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;3.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp; Please try adjust parameters of PCIe_PHY by changing the IOMUXC_GPR8 register.&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;You may refer to app note &lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&lt;A class="link-titled" href="https://www.nxp.com/docs/en/application-note/AN4784.pdf" title="https://www.nxp.com/docs/en/application-note/AN4784.pdf"&gt;https://www.nxp.com/docs/en/application-note/AN4784.pdf&lt;/A&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;&amp;nbsp;&lt;/SPAN&gt;&lt;/P&gt;&lt;P class=""&gt;&lt;SPAN class=""&gt;for details.&lt;/SPAN&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Have a great day,&lt;BR /&gt;Yuri&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 27 Nov 2017 06:53:21 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/PCIe-Phy-link-never-came-up/m-p/734574#M114342</guid>
      <dc:creator>Yuri</dc:creator>
      <dc:date>2017-11-27T06:53:21Z</dc:date>
    </item>
    <item>
      <title>Re: PCIe : Phy link never came up</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/PCIe-Phy-link-never-came-up/m-p/1208615#M167447</link>
      <description>&lt;P&gt;Hi, Pinkpr&lt;/P&gt;&lt;P&gt;I met the same proplem.Did you fix this?&lt;/P&gt;&lt;P&gt;&lt;STRONG&gt;Could you please give me a solution for this.&lt;/STRONG&gt;&lt;/P&gt;&lt;P&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Regards.&lt;/P&gt;&lt;P&gt;Wenqing&lt;/P&gt;</description>
      <pubDate>Fri, 08 Jan 2021 02:03:08 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/PCIe-Phy-link-never-came-up/m-p/1208615#M167447</guid>
      <dc:creator>Ryze</dc:creator>
      <dc:date>2021-01-08T02:03:08Z</dc:date>
    </item>
    <item>
      <title>Re: PCIe : Phy link never came up</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/PCIe-Phy-link-never-came-up/m-p/1668285#M207498</link>
      <description>&lt;P&gt;I am getting this problem &lt;SPAN&gt;intermittently.&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/103623"&gt;@pinkpr&lt;/a&gt;,&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/182033"&gt;@Ryze&lt;/a&gt;&amp;nbsp;did you tried the solution given by&amp;nbsp;&lt;a href="https://community.nxp.com/t5/user/viewprofilepage/user-id/1941"&gt;@Yuri&lt;/a&gt;&amp;nbsp;and solved the problem?&lt;/SPAN&gt;&lt;/P&gt;</description>
      <pubDate>Tue, 13 Jun 2023 09:48:09 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/PCIe-Phy-link-never-came-up/m-p/1668285#M207498</guid>
      <dc:creator>vivsundar</dc:creator>
      <dc:date>2023-06-13T09:48:09Z</dc:date>
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