i.MX Processors中的主题 Re: i.MX6ULL RM CSI interface shifted

i.MX6ULL RM CSI interface shifted

chris321 — Tue, 08 May 2018 12:33:19 GMT

according to the i.MX6ULL reference manual (p 1666/4127 ... 1673) ALT0 for

CSI_DATA00 is CSI_DATA02

CSI_DATA01 is CSI_DATA03

...

CSI_DATA07 is CSI_DATA09

thats somehow strange, shouldn't has ALT0 the same CSI data numbering as the pad name?

Re: i.MX6ULL RM CSI interface shifted

Carlos_Musich — Thu, 10 May 2018 18:46:55 GMT

Hi chris321,

As you may know each pin on i.MX devices has up to 8 potential functions, and on the other side, one function can be available in different pins.

One of the 8 functions is chosen as the "main" function and this is how the pin will be named, but it is not necessary to be ALT 0, it could be any.

Regards,

Carlos

Re: i.MX6ULL RM CSI interface shifted

chris321 — Mon, 14 May 2018 08:02:30 GMT

Hi Carlos,

I am aware that ALT0 doesn't has to be the main function and thus the pin name.

CSI_DATA00 function is not available on CSI_DATA00 pin according to the MUX table, that's whats confusing me.

Re: i.MX6ULL RM CSI interface shifted

Carlos_Musich — Mon, 14 May 2018 21:22:06 GMT

Ok ok, now I goy you.

Let me check, sounds like a typo.

Thanks Carlos

Re: i.MX6ULL RM CSI interface shifted

Carlos_Musich — Tue, 15 May 2018 15:53:13 GMT

Hi chris321,

The RM description is correct. The CSI module can support 24-bit data with DATA[9:2] multiplexed to pads CSI_DATA[07:00], DATA1 multiplexed to pad LCD_DATA16 and DATA0 multiplexed to LCD_DATA17. For more detail, please refer to the 4.1.1 Muxing Options Table. Thanks!

Regards,
Carlos
NXP Technical Support
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Re: i.MX6ULL RM CSI interface shifted

chris321 — Wed, 16 May 2018 07:00:40 GMT

Hi Carlos,

According to the table you copied from the RM the signal CSI_DATA0 is available at pin LCD_DATA17 (B13) but not available on CSI_DATA00 (E4).
Correct?

Re: i.MX6ULL RM CSI interface shifted

Carlos_Musich — Wed, 16 May 2018 15:46:12 GMT

Hi chris,

that is correct.

Re: i.MX6ULL RM CSI interface shifted

chris321 — Thu, 17 May 2018 07:16:44 GMT

Ok thank you for your time.

But I just found that in the reference schematic SPF-29364_a the signal CSI_DATA0 is connected to pin CSI_DATA00. That conflicts somehow with the above.

Re: i.MX6ULL RM CSI interface shifted

Carlos_Musich — Fri, 18 May 2018 17:48:31 GMT

Let me check.

Re: i.MX6ULL RM CSI interface shifted

Carlos_Musich — Tue, 22 May 2018 17:18:28 GMT

Hi Chris,

i.M6ULL has only 289 ball pads, all functional signals can not be escaped out at the same time, they will be multiplexed in different group pins instead. For CSI module, only CSI_MCLK, CSI_PICCLK, CSI_VSYNC, CSI_HSYNC and CSI_DATA[07:00] ball pads are defined and escaped out. As described in 4.1.1 Muxing Options table, the ball pads CSI_DATA[07:00] are mapped to the internal CSI module functional signals CSI_DATA[9:2].

On our EVK board, it uses only 8-bit CSI data lines (CSI_DATA[07:00] -> CSI_DATA[9:2]). When connect to an external 10-bit sensor, the least 2 bits are not used, and our SDK handles it in this way also. If customers want to use the full 10 bits or even more data bits, they can multiplex them to ball pads as 4.1.1 Muxing Options table.

The CSI module signal CSI_DATA0 can be multiplexed on ball pad LCD_DATA17 or UART3_RX_DATAbut not on ball pad of CSI_DATA00.

It is not so good to name the net name of CSI_DATA[07_00] ball pads connection as CSI_DATA[7:0] on the EVK schematic, but there is not typo in this RM section.

Best regards,

Carlos