MIPI DBI support on i.MX6 Solo

danielherring — Mon, 30 Oct 2017 18:52:11 GMT

On the i.mx6Solo part, the MIPI_DSI section specifically calls out both generic read/writes and DBI read/writes for DCS commands.

The System Overview section of the reference manual (42.2.1) makes it look like the DBI FIFOs which would be used for a DCS read/write are not accessible via the MIPI DSI registers defined in section 42.6.

At the moment I am trying to interlace DCS commands (reads and writes) between video packets as called out in the MIPI standards. When I send the commands with video mode enabled (MIPI_DSI_VID_MODE_CFG with en_video_mode set to 1, and vid_mode_type set to 3), I can see that the DBI read FIFO (MIPI_DSI_CMD_PKT_STATUS: dbi_pld_r_empty ) now reports not empty when I do reads, but how do I get the actual data from the FIFO?

Is there a memory area somewhere that is the DBI DCS command read and write FIFOs that is accessible?

Or is there a reason that the DCS read/writes using the generic FIFO does not work when video is enabled?

Re: MIPI DBI support on i.MX6 Solo

igorpadykov — Wed, 01 Nov 2017 09:26:40 GMT

Hi Daniel

one can look at linux drivers/video/fbdev/mxc/mipi_dsi.c for

"MIPI_DSI_CMD_MODE_CFG". DBI-2 interface is used for smart display

and command and data should be sent from IPU ASYNC port. Unfortunately

in i.MX6DQ/SDL IPU there is no support for IPU Asynchronous Interface (i.MX53 IPU

has such interface).

Best regards
igor
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i.MX ProcessorsのトピックMIPI DBI support on i.MX6 Solo

MIPI DBI support on i.MX6 Solo

Re: MIPI DBI support on i.MX6 Solo