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    <title>i.MX ProcessorsのトピックRe: SRC_GPR1 (0x020D8020) usage question (iMX6)</title>
    <link>https://community.nxp.com/t5/i-MX-Processors/SRC-GPR1-0x020D8020-usage-question-iMX6/m-p/733020#M114091</link>
    <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Lukasz&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;ROM uses some SRC_GPR registers for saving return address from low power modes, please refer to&lt;/P&gt;&lt;P&gt;Table 4-7. Persistent Bits IMX6DQ6SDLSRM_RevD.pdf on&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/docs/DOC-97660"&gt;Q&amp;amp;amp;A: How is mx6 PMIC_ON_REQ under SW control?&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Also uboot uses some of them:&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/docs/DOC-93964"&gt;How to Support Recovery Mode for POR Reboot Based on i.MX6 Android R13.4.1&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
    <pubDate>Fri, 09 Feb 2018 23:29:58 GMT</pubDate>
    <dc:creator>igorpadykov</dc:creator>
    <dc:date>2018-02-09T23:29:58Z</dc:date>
    <item>
      <title>SRC_GPR1 (0x020D8020) usage question (iMX6)</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/SRC-GPR1-0x020D8020-usage-question-iMX6/m-p/733019#M114090</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Dear All,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I'm a bit puzzled with the purpose of SRC_GPRx registers on iMX6Q SoC.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;According to the iMX6Q Applications Processor Reference Manual (IMX6DQRM.pdf rev.4):&lt;/P&gt;&lt;P&gt;Chapter 60.7.7 (page 5088), there is a NOTE:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;"&lt;STRONG&gt;This register is used by the ROM code and should not be used&lt;/STRONG&gt;&lt;BR /&gt;&lt;STRONG&gt;by application software.&lt;/STRONG&gt;"&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Could somebody explain what are the restrictions of using those registers? (SRC_GPRx)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;What I've understood from the above manual:&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Those registers keep their content during reset, so can be used as a storage of the boot count (from u-boot bootloader).&lt;/P&gt;&lt;P&gt;However, those may be as well overwritten with resume address and arguments when we go into deep power down mode(s).&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Similar question has been posed in:&lt;A href="https://community.nxp.com/thread/446851"&gt;iMX6 persistent data storage&lt;/A&gt;&amp;nbsp;, but with no reply.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;My questions:&lt;/P&gt;&lt;P&gt;1. Is it possible to reuse those registers in user application, which requires preserving data over (WDT, soft) reset?&lt;/P&gt;&lt;P&gt;2. Are there any other recommended registers for such purpose?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I've found SNVS_LPGPR (0x020CC068) - Chapter 57.9.14, which can be used in user application, but is recommended for retaining data in low-power mode(s).&lt;/P&gt;&lt;P&gt;Thread with SNVS_LPGPR usage example:&amp;nbsp;&lt;A href="https://community.nxp.com/docs/DOC-93964"&gt;https://community.nxp.com/docs/DOC-93964&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks in advance for help,&lt;/P&gt;&lt;P&gt;Łukasz Majewski&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 09 Feb 2018 10:36:33 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/SRC-GPR1-0x020D8020-usage-question-iMX6/m-p/733019#M114090</guid>
      <dc:creator>lukaszmajewski</dc:creator>
      <dc:date>2018-02-09T10:36:33Z</dc:date>
    </item>
    <item>
      <title>Re: SRC_GPR1 (0x020D8020) usage question (iMX6)</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/SRC-GPR1-0x020D8020-usage-question-iMX6/m-p/733020#M114091</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Lukasz&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;ROM uses some SRC_GPR registers for saving return address from low power modes, please refer to&lt;/P&gt;&lt;P&gt;Table 4-7. Persistent Bits IMX6DQ6SDLSRM_RevD.pdf on&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/docs/DOC-97660"&gt;Q&amp;amp;amp;A: How is mx6 PMIC_ON_REQ under SW control?&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;Also uboot uses some of them:&lt;/P&gt;&lt;P&gt;&lt;A href="https://community.nxp.com/docs/DOC-93964"&gt;How to Support Recovery Mode for POR Reboot Based on i.MX6 Android R13.4.1&lt;/A&gt;&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;BR /&gt;Note: If this post answers your question, please click the Correct Answer button. Thank you!&lt;BR /&gt;-----------------------------------------------------------------------------------------------------------------------&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Fri, 09 Feb 2018 23:29:58 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/SRC-GPR1-0x020D8020-usage-question-iMX6/m-p/733020#M114091</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2018-02-09T23:29:58Z</dc:date>
    </item>
    <item>
      <title>Re: SRC_GPR1 (0x020D8020) usage question (iMX6)</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/SRC-GPR1-0x020D8020-usage-question-iMX6/m-p/733021#M114092</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Igor,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks for the reply.&amp;nbsp;&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;The security reference manual states it clearly that I cannot write any random value to SRC_GPRx registers.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;However,&amp;nbsp; the scenario:&lt;/P&gt;&lt;P&gt;- I do use SRC_GPRx register to store bootcount (with some magic - e.g. 0xB0010002)&lt;/P&gt;&lt;P&gt;- I do boot till user space&lt;/P&gt;&lt;P&gt;- When SoC goes to power down mode those registers will be overwritten (in Linux) with proper return values&lt;/P&gt;&lt;P&gt;- We go to sleep&lt;/P&gt;&lt;P&gt;- Wakeup source is received - then BootROM uses those values to start CPUs (and bootloader is not executed)&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;For this particular scenario it&amp;nbsp;should work?&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Also in my case I do not have the battery on my PCB, so SNVS_LPGPR behaves in the same way as SRC_GPRx registers - it persists its content for WDT reset, but is cleared after POR.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Please correct me if I'm wrong, but it seems safer for me to use SNVS_LPGPR register.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Łukasz&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Sun, 11 Feb 2018 23:02:26 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/SRC-GPR1-0x020D8020-usage-question-iMX6/m-p/733021#M114092</guid>
      <dc:creator>lukaszmajewski</dc:creator>
      <dc:date>2018-02-11T23:02:26Z</dc:date>
    </item>
    <item>
      <title>Re: SRC_GPR1 (0x020D8020) usage question (iMX6)</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/SRC-GPR1-0x020D8020-usage-question-iMX6/m-p/733022#M114093</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Lukasz&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;yes for this described particular scenario it&amp;nbsp;should work.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Best regards&lt;BR /&gt;igor&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 12 Feb 2018 05:21:43 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/SRC-GPR1-0x020D8020-usage-question-iMX6/m-p/733022#M114093</guid>
      <dc:creator>igorpadykov</dc:creator>
      <dc:date>2018-02-12T05:21:43Z</dc:date>
    </item>
    <item>
      <title>Re: SRC_GPR1 (0x020D8020) usage question (iMX6)</title>
      <link>https://community.nxp.com/t5/i-MX-Processors/SRC-GPR1-0x020D8020-usage-question-iMX6/m-p/733023#M114094</link>
      <description>&lt;HTML&gt;&lt;HEAD&gt;&lt;/HEAD&gt;&lt;BODY&gt;&lt;P&gt;Hi Igor,&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;I think that I will use SNVS_LPGPR register - as I do need only single 32 bit word.&lt;/P&gt;&lt;P&gt;Moreovery, this register seems NOT to be used by BootROM, so shall be a safer choose.&lt;/P&gt;&lt;P&gt;&lt;/P&gt;&lt;P&gt;Thanks for help,&lt;/P&gt;&lt;P&gt;Best regards,&lt;/P&gt;&lt;P&gt;Łukasz&lt;/P&gt;&lt;/BODY&gt;&lt;/HTML&gt;</description>
      <pubDate>Mon, 12 Feb 2018 10:17:42 GMT</pubDate>
      <guid>https://community.nxp.com/t5/i-MX-Processors/SRC-GPR1-0x020D8020-usage-question-iMX6/m-p/733023#M114094</guid>
      <dc:creator>lukaszmajewski</dc:creator>
      <dc:date>2018-02-12T10:17:42Z</dc:date>
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